Foveated Rendering On-Chip Buffer Segmentation
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Solution Overview
Problem
Current Tile-Based Immediate Mode Rendering (TBIMR) architectures face limitations due to limited on-chip buffers, leading to incomplete render passes and inefficient data management, particularly in virtual reality applications where foveated rendering is employed, as they require frequent draining and re-tiling of data.
Innovation Solution
The implementation of a graphics processing system that includes enhanced on-chip memory management and bin comparison techniques to optimize data storage and processing, allowing for continuous render passes without the need for frequent data drainage, by utilizing multiple buffers for geometry and pointers, and integrating foveation control modules to dynamically adjust rendering quality based on fixation points.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple on-chip buffers are used for storing geometry and pointers in TBIMR architecture, then data storage capacity is improved, but device complexity increases
Solution Approach 1:
The patent divides the on-chip buffer into separate buffers for storing geometry data and pointer data. This segmentation allows each buffer to be optimized for its specific purpose, increasing overall data storage capacity while managing complexity through functional separation rather than monolithic expansion
Solution Approach 2:
The patent introduces a new dimension to the buffer structure by adding pointer buffers alongside geometry buffers. This dimensional expansion in the data storage architecture enables the system to hold more data without proportionally increasing the complexity of data management operations
2Ease of operation
If frequent draining and re-tiling of data is performed, then data management is simplified, but rendering time is increased
Solution Approach 1:
The patent implements preliminary action by pre-allocating multiple on-chip buffers before the rendering process begins. This allows the system to continuously write to different buffers without needing to drain and re-tiling during the render pass, thereby reducing rendering time while maintaining simple data management through the use of pre-prepared storage structures
Solution Approach 2:
The patent enables continuity of useful action by allowing the rendering system to continuously write geometry data to different on-chip buffers without interruption for draining operations. Multiple buffers work in parallel, eliminating the stop-start nature of single-buffer rendering and maintaining continuous productive work throughout the render pass
3Device complexity
If complete render pass is not achieved on chip, then processing requirements are reduced, but rendering quality is worsened
Solution Approach 1:
The patent segments the rendering process into multiple independent buffer operations, where each buffer can be processed separately. This segmentation allows the system to achieve complete render passes by processing multiple segments in parallel, maintaining rendering quality while managing processing requirements through concurrent operations rather than sequential processing
Data Source
AI summary
One embodiment of a virtual reality apparatus comprises: a graphics processing engine comprising a plurality of graphics processing stages, the graphics processing engine to render a plurality of image frames for left and right displays of a head mounted display (HMD); and foveation control hardware logic to independently control two or more of the plurality of graphics processing stages based on feedback received from an eye tracking module of the HMD, the feedback indicating a foveated region selected based on a current or anticipated direction of a user's gaze, the foveation control hardware logic to cause the two or more of the graphics processing stages to process the foveated region differently than other regions of the image frames.