FOWLP Capping Layer Structure for Thermal Stress Crack Resistance
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Solution Overview
Problem
Fan-out wafer level packages (FOWLPs) experience mechanical stress during assembly and usage, leading to cracks in underfill materials and other package components, causing mechanical degradation and reliability issues.
Innovation Solution
A capping layer is formed over the semiconductor package structure, including the interposer, semiconductor dies, and packaging substrate, using materials like stainless steel, copper, or gold, to mitigate thermally-induced stress and strain, thereby reducing cracking and delamination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a FOWLP assembly is subjected to mechanical stress during handling and attachment, then the package can be assembled and mounted, but cracks form in the underfill material and induce additional cracks in semiconductor die, solder material portions, interposers, and dielectric layers
Solution Approach 1:
A capping layer is formed over the semiconductor die, interposer, and packaging substrate before the assembly undergoes mechanical stress during handling and attachment. This capping layer acts as a protective cushion that absorbs and distributes mechanical stress, preventing cracks from forming in the underfill material and other package components during assembly operations
Solution Approach 2:
The patent employs a composite structure consisting of multiple materials with different mechanical properties: the capping layer (providing stress distribution), the underfill material (providing mechanical support and stress relief), and the various package components. This composite architecture allows each material to contribute its specific properties, enhancing overall crack resistance while maintaining assembly productivity
2Reliability
If the package structure is made more robust to resist mechanical stress, then crack resistance improves, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The capping layer is applied selectively to specific regions of the package structure where stress concentration is most likely to occur, such as over the semiconductor die, interposer, and packaging substrate interfaces. This localized approach provides enhanced crack resistance at critical stress points without unnecessarily increasing the complexity of the entire device structure
Solution Approach 2:
The capping layer serves as an intermediary protective element between external mechanical stress sources and the vulnerable internal package components. Rather than making all components thicker or more robust, the capping layer acts as a mediator that absorbs and distributes stress, simplifying the overall structural design while maintaining high crack resistance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The capping layer effectively counters thermally-induced mechanical degradation, enhancing the reliability and stability of the FOWLP by reducing the formation of cracks and delamination, and improving the structural integrity of the package components.
Implementation Method 1
A capping layer is formed over the semiconductor package structure, including the interposer, semiconductor dies, and packaging substrate, using materials like stainless steel, copper, or gold, to mitigate thermally-induced stress and strain
Data Source
AI summary
A disclosed semiconductor structure may include an interposer, a first semiconductor die electrically coupled to the interposer, a packaging substrate electrically coupled to the interposer, and a capping layer covering one or more of a first surface of the first semiconductor die and a second surface of the packaging substrate. The capping layer may be formed over respective surfaces of each of the first semiconductor die and the packaging substrate. In certain embodiments, the capping layer may be formed only on the first surface of the first semiconductor die and not formed over the package substrate. In further embodiments, the semiconductor structure may include a second semiconductor die, such that the capping layer covers a surface of only one of the first semiconductor die and the second semiconductor die. The semiconductor structure may include a molding compound die frame that is partially or completely covered by the capping layer.