Fan-Out Wafer-Level Package Fabrication with Laser-Stripped Release Layer
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Solution Overview
Problem
As semiconductor chip sizes increase and package thickness decreases, existing semiconductor packaging methods face challenges in achieving efficient electrical and thermal characteristics while maintaining a slim form factor, particularly with the FOWLP type semiconductor package.
Innovation Solution
A method for fabricating a semiconductor package involves forming a release layer with varying thicknesses, a barrier layer, and a redistribution layer, followed by mounting a semiconductor chip and attaching a solder ball, with the use of a laser to remove the release and barrier layers, ensuring the solder ball is electrically connected to the redistribution layer without damaging it.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If semiconductor chip size is increased to achieve high-performance element implementation, then electrical and thermal characteristics are improved, but package thickness increases and form factor becomes larger
Solution Approach 1:
The patent transitions from traditional vertical stacking to a fan-out configuration where I/O terminals are redistributed horizontally outside the chip footprint. This dimensional reorganization allows larger chip areas to be utilized for computational elements while maintaining thin package profiles by extending connectivity in the planar direction rather than increasing thickness.
Solution Approach 2:
The package structure is segmented into distinct functional layers: a thin active packaging layer containing the chip and essential interconnects, and a separate redistribution layer that handles I/O routing externally. This segmentation allows the active package thickness to remain minimal while achieving high-performance electrical and thermal characteristics through optimized material stacking and interface design.
2Reliability
If semiconductor chip size is increased, then high-performance element implementation is achieved, but semiconductor package size increases accordingly
Solution Approach 1:
The patent employs a nested structure where the semiconductor chip is embedded within a compact active package, which is then integrated with a redistribution layer that folds back over the package. This nesting allows the I/O terminals to be positioned outside the chip area without proportionally increasing the overall package footprint, effectively utilizing space in a multi-layer configuration.
Solution Approach 2:
By redistributing I/O terminals to the external surface of the package rather than requiring them to be within the chip boundaries, the patent utilizes the vertical and lateral dimensions of the package structure. This allows high-performance chips with numerous elements to maintain smaller form factors by extending connectivity to the package exterior where space is more efficiently utilized.
3Length of moving object
If FOWLP type semiconductor package is used to reduce thickness, then package thickness is reduced and thermal characteristics are improved, but achieving efficient electrical characteristics becomes challenging
Solution Approach 1:
The patent employs composite material structures in the redistribution layer and interconnect system, combining conductive materials with optimized geometric configurations. This composite approach enables efficient electrical signal routing through the thin package structure by utilizing materials and architectures that maintain low resistance and inductance despite the reduced thickness, thereby achieving both slim form factor and excellent electrical characteristics.
4Manufacturing precision
If release layer with varying thickness is formed and laser removal is used, then manufacturing precision is improved and damage to redistribution layer is prevented, but process complexity increases
Solution Approach 1:
The patent introduces a release layer with spatially varying thickness as an intermediary between the carrier substrate and the redistribution layer. This intermediate structure serves as a sacrificial element that absorbs laser energy during removal processes, protecting the underlying redistribution layer from damage while enabling precise patterning. The thickness variation of the release layer itself acts as a built-in mask, simplifying the overall process by eliminating the need for additional protective layers or complex process sequencing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the production of thin semiconductor packages with excellent thermal and electrical characteristics, facilitating the integration of larger semiconductor chips in smaller form factors.
Implementation Method 1
removing the first carrier substrate and the release layer; removing the barrier layer; and attaching a solder ball onto the redistribution layer exposed by removal of the barrier layer and the second portion of the release layer
Data Source
AI summary
A method for fabricating a semiconductor package, the method including: forming a release layer on a first carrier substrate, wherein the release layer includes a first portion and a second portion, wherein the first portion has a first thickness, and the second portion has a second thickness thicker than the first thickness; forming a barrier layer on the release layer; forming a redistribution layer on the barrier layer, wherein the redistribution layer includes wirings and an insulating layer; mounting a semiconductor chip on the redistribution layer; forming a molding layer on the redistribution layer to at least partially surround the semiconductor chip; attaching a second carrier substrate onto the molding layer; removing the first carrier substrate and the release layer; removing the barrier layer; and attaching a solder ball onto the redistribution layer exposed by removal of the barrier layer and the second portion of the release layer.