Fan-Out Wafer Level Packaging Structure Reducing Warpage
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Solution Overview
Problem
Fan-out wafer level packaging (FOWLP) results in poor performance due to stress differences between the epoxy molding compound (EMC) and silicon chips, leading to warpage and quality issues in packaged products.
Innovation Solution
A packaging structure and fabrication method where a wafer with chip regions and spacing regions is used, forming openings and molding layers that cover chip sidewalls while exposing top surfaces, reducing the volume proportion of the molding layer to minimize stress and warpage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a large volume of epoxy molding compound (EMC) is used to fully encapsulate the chips, then the chips are well protected, but stress differences cause warpage and quality issues
Solution Approach 1:
The patent divides the encapsulation space into two regions: a first encapsulation region filled with EMC that covers the sidewalls of the chips, and a second encapsulation region above the chips that remains empty or is filled with a different material. This segmentation reduces the volume of EMC used, thereby minimizing stress differences and preventing warpage while still providing adequate protection to the chips.
Solution Approach 2:
The patent applies different encapsulation strategies to different regions: the sidewall region is encapsulated with EMC for protection, while the top region is left open or filled with a different material to reduce stress. This local differentiation allows the structure to have protection where needed while avoiding warpage in the overall package.
2Length of stationary object
If the packaging structure thickness is reduced to achieve thinner packages, then packaging size is minimized, but performance deteriorates due to stress differences
Solution Approach 1:
By segmenting the encapsulation volume and reducing the EMC height, the overall package thickness is reduced while maintaining chip protection. The first encapsulation region provides necessary protection without the excessive volume that causes stress, thus improving package performance in thinner form factors.
3Shape
If the molding layer volume is reduced to minimize stress, then warpage is reduced, but chip protection may be compromised
Solution Approach 1:
The patent ensures that the first encapsulation region fully covers the sidewalls of the chips, providing adequate protection, while the second encapsulation region is reduced or eliminated. This segmentation maintains chip protection where it is most needed while reducing overall stress.
Solution Approach 2:
The patent provides concentrated protection at the chip sidewalls where mechanical support is most critical, while reducing material volume in regions where protection is less critical. This localized quality approach maintains reliability while minimizing warpage.
Data Source
AI summary
A packaging structure is provided. The packaging structure includes a plurality of first chips; and a molding layer between adjacent first chips. The molding layer covers a sidewall of the first chip and exposes a top surface of the first chip.