Fan-Out Wafer-Level Packaging with Slot-Filled Interconnects
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Solution Overview
Problem
Existing Fan-Out Wafer Level Packaging (FOWLP) technologies face high manufacturing costs, environmental unfriendliness, and lack effective electrical connections between multiple dies, while also struggling to balance electrical extension and compact design.
Innovation Solution
A FOWLP unit comprising a substrate, dies, dielectric layers, conductive circuits, bonding wires, and a protective layer, where dies are connected via bonding wires through slots in dielectric layers filled with metal paste, with exposed bonding pads for external connection, allowing for simplified manufacturing and effective electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If chemical plating or electroplating is used to form conductive circuits in the RDL, then electrical extension and interconnections are improved, but manufacturing cost increases and environmental friendliness deteriorates
Solution Approach 1:
The patent changes the formation method parameter from chemical/electro plating to screen printing with metal paste, followed by sintering. This parameter change maintains electrical conductivity while eliminating the harmful chemicals and high costs associated with traditional plating methods.
Solution Approach 2:
The patent replaces the chemical-based plating system with a mechanical screen printing system that deposits metal paste, which is then sintered to form conductive circuits. This substitution eliminates the need for chemical baths and electroplating equipment.
2Adaptability or versatility
If multiple dies are disposed in FOWLP unit to provide higher performance or more functions, then product functionality is improved, but space requirement for conductive circuits increases and manufacturing complexity increases
Solution Approach 1:
The patent extends the conductive circuits from the XY plane into the Z dimension by forming slots through the dielectric layer and filling them with conductive material. This vertical extension allows electrical connections between multiple dies stacked or adjacent to each other, reducing the horizontal space requirement.
Solution Approach 2:
The patent nests conductive circuits within slots embedded in the dielectric layer, allowing multiple layers of conductive paths to be stacked vertically. This nesting approach enables complex interconnections between multiple dies without proportionally increasing the footprint area.
3Adaptability or versatility
If multiple dies are disposed in FOWLP unit, then product performance is improved, but effective electrical connection between dies is lacking
Solution Approach 1:
The patent introduces bonding wires as intermediary elements that physically and electrically connect the bonding pads of different dies. These wires serve as mediators that bridge the electrical gap between separate die structures, enabling functional integration.
Solution Approach 2:
The patent segments the electrical connection path into distinct components: bonding pads on each die, bonding wires for inter-die connection, and conductive circuits within the substrate. This segmentation allows flexible routing and reliable connections between multiple independent dies.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces manufacturing costs, enhances environmental sustainability, and ensures effective electrical connections between dies, maintaining a slim and reliable packaging design.
Implementation Method 1
The conductive circuits are formed by a metal paste filled in a plurality of first slots of the first dielectric layer and a plurality of second slots of the second dielectric layer
Implementation Method 2
The first bonding wire forms a first bonding point and a second bonding point on the two first bonding pads correspondingly of the respective dies by a wire bonding process
Data Source
AI summary
A fan-out wafer-level packaging (FOWLP) is provided. The FOWLP unit includes a substrate, at least two dies, a first dielectric layer, a second dielectric layer, a plurality of conductive circuits, at least two first bonding pads, at least one first bonding wire, and an outer protective layer. The dies are electrically connected to each other by the first bonding wire. The respective conductive circuits are formed by a metal paste filled in first slots of the first dielectric layer and second slots of the second dielectric layer. A second bonding pad is formed in respective openings of the outer protective layer. The die is electrically connected to the outside by the second bonding pad around a chip area above the second surface of the die. Thereby problems of conventional FOWLP generated during manufacturing of conductive circuits including higher manufacturing cost and less environmental benefits are solved.