3D Fanout Wafer Level Package Stacking for Z-Height Reduction
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Solution Overview
Problem
Current semiconductor packaging technologies face challenges in achieving higher I/O counts and smaller sizes for integrated circuit (IC) die, particularly in package-on-package (PoP) applications, due to limitations in fan-out wafer level packaging that restricts the integration of multiple components and increases package z-height.
Innovation Solution
The development of fan-out wafer level packages (FOWLPs) that involve stacking redistribution layers with conductive pillars, allowing for the integration of multiple components and reducing package z-height by forming a FOWLP within a FOWLP structure, where each layer is encapsulated with molding compounds to optimize space and I/O density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional packaging technologies are used to achieve higher I/O counts, then the I/O count increases, but the package z-height increases
Solution Approach 1:
The patent implements a nested structure where a first FOWLP package is integrated within a second FOWLP package. The first package includes its own die, molding compound, and conductive pillars, which are then embedded within the second package's molding compound. This nesting approach allows multiple I/O interfaces to be stacked vertically rather than spread horizontally, increasing I/O count while maintaining compact z-height dimensions.
Solution Approach 2:
The patent transitions from conventional 2D package layouts to 3D stacked architecture by utilizing the vertical dimension. Multiple routing layers are stacked with conductive pillars extending between them, creating a three-dimensional integration scheme. This dimensional change enables higher I/O counts by distributing I/O interfaces across multiple vertical layers rather than confining them to a single plane.
2Adaptability or versatility
If multiple components are integrated in conventional packaging, then component integration increases, but device complexity increases
Solution Approach 1:
The patent divides the integrated package into distinct modular segments: a first FOWLP package with its own die, routing layer, and molding compound, and a second FOWLP package that encapsulates the first. Each segment is independently fabricated and then integrated through the molding compound bonding process. This segmentation allows complex multi-component integration while maintaining manageable complexity through standardized module repetition.
Solution Approach 2:
The patent employs universal FOWLP building blocks that can serve multiple functions. The same FOWLP structure with die, routing layer, and molding compound can be replicated and stacked to create different multi-component packages. This universality enables flexible component integration without requiring unique complex structures for each configuration, as the standardized FOWLP module can be adapted for various integration scenarios.
Data Source
AI summary
Fanout wafer level packages (FOWLPs) and methods of formation are described. In an embodiment, a package includes a first routing layer, a first die on a top side of the first routing layer, and a first molding compound encapsulating the first die on the first routing layer. A first plurality of conductive pillars extends from a bottom side of the first routing layer. A second die is on a top side of a second routing layer, and the first plurality of conductive pillars is on the top side of the routing layer. A second molding compound encapsulates the first molding compound, the first routing layer, the first plurality of conductive pillars, and the second die on the second routing layer. In an embodiment, a plurality of conductive bumps (e.g. solder balls) extends from a bottom side of the second routing layer.