Fan-Out Wafer Level Package Substrate Routing
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Solution Overview
Problem
Current semiconductor die packaging technologies face challenges in improving yield, reducing physical volume, and enhancing performance, including high complexity and costs associated with routing layers and the need for printed circuit boards.
Innovation Solution
The introduction of a semiconductor device with a first routing layer coupled to the semiconductor die, featuring a substrate with routing traces, which reduces the complexity of the second routing layer and allows for testing before further manufacturing operations, thereby improving yield and reducing physical volume by increasing density without the need for a printed circuit board.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If traditional semiconductor die packaging with multiple routing layers and printed circuit boards is used, then signal routing capability is achieved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent extracts and eliminates the printed circuit board from the packaging structure, integrating routing functions directly into the substrate. This removes the complex multi-layer PCB architecture while maintaining signal routing capability through substrate-integrated traces and vias, thereby reducing overall device complexity without compromising reliability
Solution Approach 2:
The patent merges the routing layer functions with the substrate structure itself, combining what were previously separate components (substrate and routing layers) into a unified integrated substrate architecture. This consolidation reduces the number of discrete layers and interfaces, simplifying the overall packaging structure while improving manufacturing yield
2Volume of moving object
If traditional packaging with printed circuit board is used, then signal routing is achieved, but physical volume increases
Solution Approach 1:
The patent implements a nested architecture where the semiconductor die is embedded within the substrate, and routing traces are integrated within the substrate layers. This nesting eliminates the need for a separate printed circuit board, as the substrate itself contains both the device and the routing infrastructure, significantly reducing packaging volume while maintaining structural integrity
Solution Approach 2:
The patent transitions from a traditional planar PCB-based routing approach to a three-dimensional substrate-integrated routing architecture. By utilizing vertical vias and multi-layer substrate routing, the design achieves complex signal paths in a compact volume, effectively moving routing functionality into the vertical dimension rather than requiring extensive horizontal PCB area
3Productivity
If testing is performed after complete manufacturing, then manufacturing process is simple, but yield improvement is limited
Solution Approach 1:
The patent enables testing operations to be performed at intermediate stages during the manufacturing process, rather than only after complete assembly. By designing the substrate and routing structure to allow access and measurement points during fabrication, the process enables early detection of defects, allowing for yield improvement while maintaining manufacturing efficiency through progressive quality control
Data Source
AI summary
An electronic device may include a semiconductor die. The electronic device may include a first routing layer. The first routing layer may be coupled to the semiconductor die. A first plurality of routing traces may be in electrical communication with the semiconductor die. The first plurality of routing traces may be positioned within a first routing footprint. The first routing footprint may have a width greater than a width of the semiconductor die.A second routing layer may be coupled to the first routing layer. A second plurality of routing traces may be in electrical communication with the first plurality of routing traces. The second plurality of routing traces may be positioned within a second routing footprint. The second routing footprint may have a width greater than the width of the first routing footprint.