Fan-out Wafer Level Package Trace Width Variation
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Solution Overview
Problem
In fan-out wafer level package structures, traces near the edge region of the chip are prone to breaking due to differences in thermal expansion and contraction between the chip and the molding compound, leading to potential failures during temperature variations.
Innovation Solution
The design includes traces with varying widths, with a wider first portion at the edge region and a narrower second portion, or the incorporation of reinforcement members on the dielectric layer to provide enhanced support and disperse stress, thereby reducing the likelihood of trace breakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traces are formed on the dielectric layer near the junction of the chip and molding compound, then the fan-out wafer level package structure can be completed with circuit connections, but the traces are easily broken due to thermal expansion differences between the chip and molding compound
Solution Approach 1:
The trace width is varied along its length, with the first portion (near the chip edge) having a larger width than the second portion (toward the center). This local variation in geometric property provides enhanced mechanical strength and stress resistance at the critical location where thermal expansion stress is most severe, while maintaining standard trace dimensions in less critical areas.
Solution Approach 2:
The reinforcement member is pre-installed on the dielectric layer at the edge region before the trace is formed or alongside it. This reinforcement member acts as a protective cushion that absorbs and distributes the thermal expansion stress before it can concentrate on and break the trace, thereby preventing failure in advance.
2Strength
If the trace width is increased at the edge region to improve strength, then the trace becomes more resistant to breaking, but the overall trace geometry becomes more complex
Solution Approach 1:
Instead of uniformly increasing the trace width throughout, the design applies the width variation only to the first portion at the edge region. This localized geometric modification provides the necessary strength enhancement precisely where thermal expansion stress is most severe, while keeping the rest of the trace geometry simple and easy to manufacture.
3Reliability
If reinforcement members are added to the dielectric layer at the edge region, then the traces gain enhanced support and stress dispersion, but the device structure becomes more complex
Solution Approach 1:
The reinforcement member is positioned on the dielectric layer at the edge region to provide preemptive mechanical support. It functions as a cushioning element that absorbs and distributes thermal expansion stress before it can concentrate on the trace, thereby preventing breakage. The reinforcement member can be integrated into the existing package structure without requiring fundamental redesign.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the strength of traces near the edge region and improves the durability of the fan-out wafer level package structure by mitigating stress caused by thermal expansion mismatches, resulting in better resistance to temperature-induced failures.
Implementation Method 1
The molding compound encapsulates the chip
Implementation Method 2
traces are formed on the active surface of the chip and the molding compound to pull out contacts of the chip to the molding compound through the traces
Implementation Method 3
the reinforcement members are configured on the dielectric layer at the edge region of the projection of the chip onto the dielectric layer to provide enhanced support for the traces near the edge region
Implementation Method 4
due to the difference in thermal expansion coefficients of the chip and the molding compound, the degrees of thermal expansion and contraction between different components
Data Source
AI summary
A fan-out wafer level package structure includes a chip, a molding compound, at least one circuit layer, and at least one dielectric layer. The molding compound encapsulates the chip. The at least one circuit layer is disposed on a surface of the chip and a surface of the molding compound coplanar to the surface of the chip. The at least one circuit layer includes a plurality of traces. Each of the traces includes a first portion and a second portion. The first portion is located at an edge region of a projection of the chip onto the dielectric layer. A width of the first portion is larger than a width of the second portion. The at least one dielectric layer is disposed at a side of the at least one circuit layer.