Fan-Out Wafer-Level Packaging Eliminates TSVs
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Solution Overview
Problem
Current fan-out wafer-level packaging methods face challenges such as high assembly costs due to the need for Through Silicon Vias (TSVs) and limited scalability, as well as issues with package yield and I/O pitch alignment, which are not adequately addressed by existing technologies like the 2.5D Si interposer solution.
Innovation Solution
A method involving a silicon substrate with active and passive devices formed on a FEOL layer, followed by copper damascene formation of metallization layers for redistribution, and thinning of the substrate to create silicon regions, eliminating the need for TSVs and enabling integration of devices into the Si substrate without recycling constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 2.5D Si interposer solution is used to achieve high density interconnection, then I/O density is improved, but assembly cost increases due to TSV fabrication requirements
Solution Approach 1:
The patent extracts and eliminates the TSV fabrication step from the interconnection process. By using a silicon carrier with through-holes filled with conductive material instead of TSVs, the complex TSV fabrication process is removed while maintaining high density interconnection capability, thereby reducing assembly cost
Solution Approach 2:
The patent employs a disposable silicon carrier that is removed after bonding. This carrier enables high density interconnection during assembly but is discarded afterward, avoiding the need for expensive permanent TSV structures while achieving the desired I/O density
2Ease of manufacture
If Si wafer is used in SLIT to eliminate TSVs, then fabrication cost is reduced, but Si wafer cannot be recycled increasing overall cost
Solution Approach 1:
The patent recovers and reuses the silicon carrier wafer after the bonding process. The carrier is cleaned and prepared for subsequent bonding cycles, transforming it from a disposable component into a reusable tooling element, thereby eliminating waste and reducing overall manufacturing cost
3Volume of moving object
If conventional FOWLP methods are used, then package size is reduced, but package yield is dominated by RDL yield and I/O pitch is limited by alignment mismatching
Solution Approach 1:
The patent performs preliminary alignment and bonding of IC dies to the silicon carrier before RDL formation. By establishing precise mechanical alignment upfront through the carrier structure, subsequent RDL patterning can achieve better alignment accuracy, improving package yield without sacrificing miniaturization
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces fabrication costs by eliminating TSVs, enhances I/O density, and improves package reliability by integrating devices directly into the silicon substrate, allowing for finer pitch interconnects without the need for TSVs, thus addressing the limitations of existing methods.
Implementation Method 1
forming a redistribution layer (RDL) over the FEOL layer by copper damascene formation of multiple metallization layers
Data Source
AI summary
A fan-out wafer-level packaging method and the package produced thereof are provided in the present application. The method comprises steps including: providing a silicon substrate layer having a first thickness; forming one or more active/passive devices comprising at least sources and drains and one or more diffusion layers adjoining the sources and drains, wherein forming the one or more active/passive devices comprises forming the sources and the drains in a front-end-of-line (FEOL) layer on a first side of the silicon substrate layer while forming the one or more diffusion layers at locations in the silicon substrate layer adjoining the sources and the drains; forming a redistribution layer (RDL) over the FEOL layer by copper damascene formation of multiple metallization layers for connecting the one or more active/passive devices to the one or more IC dies when the one or more IC dies are mounted on a side of the RDL opposite the FEOL layer; thinning the silicon substrate layer to a second thickness to form a thinned silicon substrate, the thinned silicon substrate comprising at least the one or more diffusion layers; and patterning the thinned silicon substrate to form one or more silicon regions, each of the one or more silicon regions comprising the one or more diffusion layers.