FOWLP Module Wire-Bond Layout Without Plating Circuits
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Solution Overview
Problem
The existing Fan-Out Wafer Level Packaging (FOWLP) technology faces challenges in balancing electrical extension and interconnections of conductive circuits, leading to increased manufacturing costs and environmental impact, particularly in multi-chip designs.
Innovation Solution
A module comprising a FOWLP unit connected by wire bonding, featuring a substrate, dies, dielectric layers, conductive circuits, and bonding pads, formed using metal paste in slots, with bonding wires connecting dies and electronics, simplifying the manufacturing process and reducing material costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If chemical plating or electroplating is used to form conductive circuits in the RDL, then electrical extension and interconnections are improved, but manufacturing cost increases and environmental impact worsens
Solution Approach 1:
The patent changes the material state and formation method of conductive circuits from electrochemical plating to screen printing with metal paste. This parameter change in manufacturing technique eliminates the need for chemical plating solutions and electroplating processes, thereby reducing manufacturing cost and environmental impact while maintaining electrical conductivity through the metal paste formulation and firing process
Solution Approach 2:
The patent replaces the electrochemical system (chemical plating/electroplating) with a mechanical printing system (screen printing). The screen printing process uses a mesh template to deposit metal paste precisely where needed, substituting the complex electrochemical deposition process with a simpler mechanical transfer method that is more cost-effective and environmentally friendly
2Adaptability or versatility
If at least two dies are disposed in FOWLP unit to provide higher performance or more functions, then functionality is improved, but space required for conductive circuits increases and manufacturing complexity increases
Solution Approach 1:
The patent divides the multi-die FOWLP unit into modular components with standardized bonding pad arrangements. Each die is designed with distributed bonding pads around the chip area, allowing independent placement and connection. This segmentation enables flexible configuration of multiple dies while simplifying the overall manufacturing process through standardized interconnection patterns
Solution Approach 2:
The patent transitions from planar circuit routing to three-dimensional vertical stacking by arranging bonding pads around the chip area in multiple directions. This dimensional change allows conductive circuits to extend in the XY plane more effectively, providing multiple interconnection paths for multi-die configurations without increasing lateral space requirements, thereby reducing manufacturing complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances electrical connections, reduces manufacturing costs, and improves environmental sustainability while maintaining a compact and reliable design, enabling higher performance and functionality in module products.
Implementation Method 1
at least one first bonding wire (90) and at least two second bonding wires (100); The first bonding wire (90) forms a first bonding point (91) and a second bonding point (92) on the bonding pads (70) of the dies (20) by a wire bonding process
Data Source
AI summary
A module containing a fan-out wafer-level packaging (FOWLP) unit connected to an electronic by wire bonding is provided. The module includes a FOWLP unit, an electronic, at least one first bonding wire, and at least two second bonding wires. The FOWLP unit includes a substrate, at least two dies, a first dielectric layer, a second dielectric layer, a plurality of conductive circuits, an outer protective layer, and a plurality of bonding pads. The conductive circuits are formed by a metal paste filled in first slots of the first dielectric layer and second slots of the second dielectric layer. At least one of the bonding pads is located around a chip area on a second surface of the dies to be electrically connected to the outside. Thereby problems of FOWLP modules available now including higher manufacturing cost and less environmental benefits can be solved.