FOXFET ESD Clamp Layout for Lower Trigger Voltage
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Solution Overview
Problem
Conventional electrostatic discharge (ESD) clamp circuits in semiconductor devices have high trigger voltage and on-resistance, which can lead to temporary or permanent damage to semiconductor devices due to the long discharging current path from the power-supply terminal to the ground terminal.
Innovation Solution
An ESD protection device is designed with a P-type semiconductor substrate, N-type and P-type well regions, N-type and P-type doped regions, an isolation feature, and a conductive plate, forming an N-type field-oxide field-effect transistor (FOXFET) that reduces the on-resistance by creating a shorter current path during ESD events, thereby lowering the trigger voltage and on-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a conventional ESD clamp circuit is used with a long discharging current path from power-supply terminal to ground terminal, then the circuit structure is simple and easy to manufacture, but the on-resistance is high and trigger voltage is high
Solution Approach 1:
The ESD protection device is segmented into multiple functional regions: N-type well region, P-type well region, first N-type doped region, second N-type doped region, and first P-type doped region. Each region serves a specific function in creating the discharge path, allowing optimization of the current path length and resistance characteristics while maintaining manufacturing feasibility through standardized region-based fabrication processes
Solution Approach 2:
The patent introduces a vertical stacking dimension by placing the conductive plate above the P-type well region and using overlapping configurations between doped regions and wells. This three-dimensional arrangement shortens the horizontal current path while maintaining electrical isolation, effectively reducing on-resistance without extending the lateral footprint of the device
2Reliability
If the discharging current path is shortened to reduce on-resistance and trigger voltage, then the reliability is improved, but the device complexity increases
Solution Approach 1:
The P-type well region serves multiple functions: it provides the substrate for the conductive plate, forms part of the discharge path between doped regions, and enables the overlapping configuration that shortens the current path. The conductive plate simultaneously acts as an electrode and a structural element that defines the vertical field distribution, reducing the need for additional components
Solution Approach 2:
The device employs a nested configuration where the first P-type doped region is positioned within the P-type well region, and the conductive plate is positioned above the P-type well region with overlapping geometry. This nesting creates a compact vertical structure that shortens the effective discharge path while maintaining electrical isolation between regions through the well structures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The ESD protection device effectively reduces the on-resistance and trigger voltage, enhancing the reliability and service life of semiconductor devices by providing a more efficient discharge path for electrostatic charges.
Implementation Method 1
an N-type field oxide field-effect transistor (FOXFET) that reduces the on-resistance by creating a shorter current path during ESD events
Implementation Method 2
an electrostatic discharge path that effectively protects the semiconductor device
Data Source
AI summary
An electrostatic discharge protection device is provided. The electrostatic discharge protection device includes a P-type semiconductor substrate, N-type and P-type well regions, first and second N-type doped regions, a first P-type doped region and a first conductive plate. The N-type and P-type well regions are located in the P-type semiconductor substrate and are adjacent to each other. The first N-type doped region located on the N-type well region is spaced apart from the second N-type doped region located on the P-type well region by an isolation feature. The first P-type doped region located on the P-type well region is spaced apart from the second N-type doped region. The first conductive plate overlaps the isolation feature. The first N-type doped region and the first conductive plate are electrically connected to a power-supply terminal. The second N-type and first P-type doped regions are electrically connected to a ground terminal.