Floating Point Add Low Functional Unit for High Precision Arithmetic
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Solution Overview
Problem
Conventional processors face inefficiencies in performing floating-point arithmetic operations, particularly in applications requiring high precision, as native floating-point precision is often insufficient, leading to increased latency and performance degradation due to the need for software emulation of multi-precision operations.
Innovation Solution
The implementation of hardware-based ADD low operations, which break down a full ADD operation into a sum of high and low floating-point values, allowing for exact results with reduced rounding errors and increased efficiency by minimizing the number of floating-point operations required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If software emulation is used to perform multi-precision floating-point operations, then measurement precision is improved, but productivity deteriorates due to increased latency and number of operations required
Solution Approach 1:
The floating-point addition operation is segmented into two distinct hardware units: a first functional unit that computes the sum of two floating-point numbers, and a second functional unit that computes the difference between the computed sum and the rounded sum. This segmentation allows each unit to be optimized for its specific function, enabling multi-precision results without requiring software emulation sequences.
Solution Approach 2:
The patent introduces an intermediary mechanism where the first functional unit's output (the sum) is immediately fed into the second functional unit along with the rounded sum from the rounding unit. This intermediary computation step (computing the difference) serves as a mediator to extract the low-order precision bits, providing high-precision results through hardware rather than software mediation.
2Device complexity
If conventional floating-point addition is used, then device complexity is reduced, but manufacturing precision deteriorates due to insufficient precision for certain applications
Solution Approach 1:
The addition operation is divided into two independent but coordinated functional units. The first unit handles the standard floating-point addition, while the second unit handles the precision correction by computing the difference between the actual sum and the rounded sum. This segmentation enables high-precision results without requiring a complete redesign of the floating-point unit architecture.
Solution Approach 2:
The patent performs a partial computation in the second functional unit - specifically computing only the difference between the sum and rounded sum, rather than performing a complete addition. This partial action is sufficient to extract the low-order precision bits needed for high-precision applications, avoiding the need for full multi-precision addition hardware.
3Measurement precision
If more floating-point operations are performed to achieve high precision, then measurement precision is improved, but use of energy increases
Solution Approach 1:
The second functional unit performs only a partial computation - calculating the difference between the sum and rounded sum - which is exactly sufficient to obtain the low-order precision bits. This avoids performing unnecessary additional floating-point operations that would consume extra power, achieving high precision with minimal computational overhead.
Solution Approach 2:
By segmenting the precision enhancement into a dedicated second functional unit that performs only the necessary difference computation, the patent avoids requiring multiple full floating-point operation sequences. This segmentation enables precision improvement with localized, energy-efficient hardware rather than repeated energy-intensive software emulation steps.
Data Source
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AI summary
An example processor includes a register and an ADD low functional unit. The register stores first, second, and third floating point (FP) values. The ADD low functional unit receives a request to perform an ADD low operation and, responsive to the request: adds the first FP value with the second FP value to obtain a first sum value; rounds the first sum value to generate an ADD value; adds the first FP value with the second FP value to obtain a second sum value; subtracts the ADD value from the second sum value to generate a difference value; normalizes the difference value to obtain a normalized difference value; rounds the normalized difference value to generate an ADD low value; and sends the ADD low value to an application.