Floating Point Dot Product Multiplier-Accumulator Pipelined Architecture
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Solution Overview
Problem
Existing integer architectures face scalability issues in performing dot product computations between large floating-point matrices, leading to increased complexity and power consumption due to the high number of multiplication and addition operations required.
Innovation Solution
A pipelined floating-point multiplier-accumulator architecture that separates sign, exponent, and mantissa components of input and coefficient values, performs exclusive OR operations, normalizes mantissa products, and adjusts exponents to efficiently compute dot products, utilizing multiple pipeline stages for concurrent processing and minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If prior art integer architectures are used for dot product computations, then the number of multiplication and addition operations scales as the product of n and m, but the complexity becomes much greater for signed floating point multiplication operations
Solution Approach 1:
The floating point multiplication is segmented into three independent processing stages: sign processing (XOR operation), exponent processing (addition and difference calculation), and mantissa processing (integer multiplication). Each stage handles a specific component of the floating point numbers, allowing parallel processing and reducing overall computational complexity.
Solution Approach 2:
The patent introduces intermediate values including exponent difference (EXP_DIFF = MAX_EXP - exponent_sum), normalized mantissa, and integer form fraction as intermediaries to transform the complex floating point multiplication into simpler integer-based operations that can be efficiently computed and then recombined.
2Productivity
If the number of multiplication and addition operations increases for large matrices, then dot product computations can be performed, but power consumption increases
Solution Approach 1:
By segmenting the computation into parallel pipeline stages that process multiple floating point operations simultaneously, the patent reduces the total number of sequential operations required, thereby reducing power consumption while maintaining computational capability for large matrices.
Solution Approach 2:
The patent replaces complex floating point multiplication mechanics with simpler integer multiplication mechanics for the mantissa component, using XOR for sign processing and addition for exponent processing, which are less power-intensive operations.
3Speed
If a pipelined architecture is used for floating point multiplication, then high-speed computations are achieved, but the device complexity increases
Solution Approach 1:
The pipeline is segmented into distinct functional stages (sign processor, exponent processor, mantissa processor) that can be independently implemented and optimized, allowing high-speed parallel processing while managing complexity through modular design.
Solution Approach 2:
Multiple processing operations are merged into unified pipeline stages where sign, exponent, and mantissa processing occur in an integrated flow, reducing overall architecture complexity compared to separate processing units for each component.
Data Source
AI summary
A vector dot product multiplier receives a row vector and a column vector as floating point numbers in a format of sign plus exponent bits plus mantissa bits. The dot product multiplier generates a single dot product value by separately processing the sign bits, exponent bits, and mantissa bits in a few pipelined stages. A first pipeline stage generates a sign bit, a normalized mantissa formed by multiplying pairs multiplicand elements, and exponent information. A second pipeline stage receives the multiplied pairs of normalized mantissas, performs an adjustment, performs a padding, complement, and shift, and sums the results in an adder stage. The resulting integer is normalized to generate a sign bit, exponent, and mantissa of the floating point result.