Floating-Point Multiplier Rounding Circuit for Shorter Critical Paths
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The rounding calculation in prior art always adds to the critical path in some fashion, making it inefficient for floating point multiplication, which results in a temporary mantissa with more bits of precision than can be stored, requiring specific rounding modes to be defined for IEEE floating point specifications.
Innovation Solution
The solution simultaneously calculates the mantissa values for no rounding, rounding up with no additional left shift, and rounding up with an additional left shift, reducing the critical timing path by combining instances where the 2K term may be added, and using RTL code to generate the mantissa values efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If rounding calculation is performed sequentially after multiplication, then correct IEEE floating point rounding is achieved, but the critical path delay increases
Solution Approach 1:
The patent calculates the three possible mantissa values (no rounding, round up with no shift, round up with shift) in parallel during the multiplication operation itself, rather than sequentially after. This preliminary calculation of all possible rounding outcomes eliminates the need for sequential rounding operations, reducing critical path delay while ensuring correct IEEE floating point rounding through selective use of pre-calculated values based on the rounding mode and exponent comparison
2Adaptability or versatility
If multiple rounding mode calculations are performed separately, then all IEEE rounding modes are supported, but the circuit complexity and timing path increase
Solution Approach 1:
The patent merges the calculation of three different rounding outcomes into a single unified circuit structure. Instead of implementing separate rounding circuits for each IEEE rounding mode (round to nearest, round toward zero, round toward positive infinity, round toward negative infinity), the invention calculates all possible mantissa values simultaneously using shared hardware resources, including common adders and multiplexers that select the appropriate result based on the rounding mode and exponent comparison, thereby reducing overall circuit complexity
Data Source
AI summary
An optimized floating point multiplier rounding circuit that minimizes the increase of the critical timing path of the calculation. The values of the temporary mantissa required to make the rounding decision are calculated simultaneously by the circuit shown in the invention.