Floating-Point Renaming Register Release Mechanism
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Solution Overview
Problem
In high-performance computing applications, arithmetic processors that perform out-of-order execution of instructions face performance degradation due to the shortage of floating-point renaming registers, leading to increased execution time and decoding stoppages, especially when exceptions occur during floating-point operations.
Innovation Solution
The arithmetic processor includes an instruction completion controller circuit that releases renaming registers early, allowing for out-of-order execution and reducing the allocation time of renaming registers by configuring exception handling to not perform at instruction completion, thereby preventing shortages and improving execution efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the arithmetic processor waits for floating-point operation termination before releasing renaming registers, then exception handling is ensured, but renaming register shortage occurs and execution time increases
Solution Approach 1:
The patent applies preliminary action by releasing renaming registers before the floating-point operation actually terminates. The instruction completion controller circuit releases the renaming register allocation at an earlier timing (when the instruction is decoded or dispatched) rather than waiting for the operation to complete, thereby preventing register shortage and reducing execution time while maintaining exception handling capability through alternative mechanisms
2Productivity
If the arithmetic processor releases renaming registers early without waiting for operation termination, then execution efficiency improves, but exception handling capability is compromised
Solution Approach 1:
The patent segments the register release process into two independent parts: (1) renaming register release controlled by the instruction completion controller circuit that occurs early to improve efficiency, and (2) exception status tracking handled separately by the floating-point operation circuit that maintains reliability. This segmentation allows both goals to be achieved simultaneously without interference
3Extent of automation
If the arithmetic processor allocates renaming registers for each floating-point operation, then out-of-order execution is enabled, but renaming register shortage occurs due to long allocation time
Solution Approach 1:
The patent applies preliminary action by performing renaming register allocation at the instruction decode or dispatch stage rather than waiting until operation completion. The instruction completion controller circuit is configured to release renaming registers early, thereby reducing the allocation time and preventing register shortage that would otherwise occur during long floating-point operations
Solution Approach 2:
The patent implements dynamic register management where the instruction completion controller circuit dynamically releases renaming registers based on instruction completion status rather than using static allocation. This dynamic approach allows the system to adapt register availability to actual execution needs, enabling out-of-order execution while minimizing allocation time
Data Source
AI summary
An arithmetic circuit performs a floating-point operation. A floating-point register includes entries each allocated to an architectural register or a renaming register. An operation execution controller circuit issues a floating-point operation instruction and outputs a termination report of the floating-point operation before the floating-point operation is terminated. When exception handling is not performed at the time of instruction completion even when an exception is detected in the operation of the floating-point operation instruction, an instruction completion controller circuit outputs a release instruction that indicates a release of a renaming register when instruction execution is completed after the termination report is received. An instruction decoder circuit receives the release instruction, allocates a first entry allocated to an architectural register that stores an execution result of the floating-point operation to a renaming register, and allocates a second entry allocated to a renaming register in the floating-point operation to the architectural register.