Floating-Point Processor Subprecision Power Gating
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Solution Overview
Problem
Floating-point processors often consume excessive power due to fixed precision formats, which is inefficient for applications requiring varying levels of precision, particularly in battery-operated devices where power management is crucial.
Innovation Solution
A floating-point processor with a selectable subprecision format that allows for the reduction of precision based on specific operations, using a floating-point controller to remove power from components handling excess bits, thereby optimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the floating-point processor uses full precision format (e.g., 32-bit or 64-bit IEEE-754), then the precision and accuracy of calculations are improved, but the power consumption increases
Solution Approach 1:
The patent implements dynamic precision selection where the floating-point processor can switch between full precision and reduced subprecision modes based on application requirements. The controller dynamically adjusts the number of mantissa bits used (e.g., from 23 bits to fewer bits) to match the actual precision needs, thereby reducing power consumption when full precision is not required while maintaining high precision when needed.
Solution Approach 2:
The patent changes the parameter of mantissa bit depth from a fixed value to a variable parameter that can be adjusted between different precision levels. By modifying the number of active mantissa bits (e.g., using only 10-16 bits instead of 23 bits for graphics applications), the processor adapts its precision to match application demands, directly reducing power consumption proportionally to the reduction in active bits.
2Measurement precision
If the floating-point processor is designed for fixed high precision, then the accuracy for applications requiring high precision (e.g., GPS) is maintained, but the power consumption increases for applications that do not require such precision (e.g., 3D graphics)
Solution Approach 1:
The patent makes the floating-point processor universal by enabling it to serve multiple application types with different precision requirements using the same hardware. The processor can function as a high-precision unit for GPS calculations when needed, and as a lower-precision unit for 3D graphics rendering when appropriate, thereby achieving multi-functionality without requiring separate dedicated processors for each application type.
Solution Approach 2:
The processor dynamically adapts its precision level to match the specific application requirements. The controller receives instructions indicating the desired precision level and adjusts the active mantissa bits accordingly, allowing the same physical processor to optimize performance for diverse applications ranging from high-precision scientific calculations to lower-precision graphical computations.
3Measurement precision
If the floating-point processor uses more bits in the mantissa, then the precision and accuracy are improved, but the power consumption and device complexity increase
Solution Approach 1:
The patent segments the mantissa into multiple portions that can be independently activated or deactivated based on precision requirements. Instead of treating the 23-bit mantissa as a single fixed unit, the processor divides it into variable segments, activating only the necessary number of bits (e.g., using only the most significant 12-16 bits for graphics applications), thereby simplifying the active circuitry and reducing complexity while maintaining sufficient precision.
Data Source
AI summary
A method and apparatus for performing a floating-point operation with a floating-point processor having a given precision is disclosed. A subprecision for the floating-point operation on one or more floating-point numbers is selected. The selection of the subprecision results in one or more excess bits for each of the one or more floating-point numbers. Power may be removed from one or more components in the floating-point processor that would otherwise be used to store or process the one or more excess bits, and the floating-point operation is performed with power removed from the one or more components.