FP16-to-BF8 Instruction Conversion for AI Memory Bandwidth

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing processors face inefficiencies in converting half-precision floating-point data to 8-bit floating-point data, leading to memory utilization and bandwidth issues, and current methods are slow and cumbersome, affecting performance and precision in AI computations.

Innovation Solution

Implementing specialized instructions, such as VCVTNEPH2BF8 and VCVTNE2PH2BF8, to directly convert packed FP16 data to BF8 data using IEEE nearest even rounding, optimizing hardware to perform this conversion efficiently and hiding it from software and operating systems.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If conventional conversion methods are used to convert FP16 to BF8, then the conversion can be performed, but the conversion speed is slow and memory bandwidth is insufficient

Engineering Contradiction:
Improveconversion speedVSAvoidmemory bandwidth utilization
Core Design Contradiction:
SpeedVSProductivity

Solution Approach 1:

The patent segments the conversion process into distinct hardware units: an FP16 to integer conversion unit that converts FP16 data to 32-bit integers, and a BF8 conversion unit that converts the integers to BF8 format. This segmentation allows parallel processing and optimizes the conversion pipeline for speed.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces 32-bit integer data as an intermediary format in the conversion pipeline. The FP16 data is first converted to 32-bit integers, which then serve as the input for BF8 conversion. This intermediary representation simplifies the conversion process and enables more efficient hardware implementation.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If FP16 data is converted to BF8 using existing methods, then the conversion can be completed, but the process is cumbersome and affects performance

Engineering Contradiction:
Improvecompute operation performanceVSAvoidconversion process complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent merges the FP16 to BF8 conversion process with the existing integer conversion pipeline. By combining these operations into a unified hardware structure, the patent reduces the number of separate conversion steps and improves overall compute operation performance.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The conversion hardware is designed to automatically perform the FP16 to BF8 conversion as part of the normal data processing pipeline, without requiring separate software intervention or complex multi-step processes. The hardware self-services the conversion need efficiently.

Inventive Principle:
Principle #25Self-service

3Quantity of substance

If standard conversion approaches are used, then the conversion can be performed, but memory footprint is large and bandwidth issues occur

Engineering Contradiction:
Improvememory footprintVSAvoiddata transfer speed
Core Design Contradiction:
Quantity of substanceVSSpeed

Solution Approach 1:

The patent changes the data representation parameters during conversion, transforming FP16 format (16 bits) to BF8 format (8 bits). This parameter change reduces the memory footprint by half while maintaining the essential numerical information needed for AI computations.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS12367045B2Instructions to convert from FP16 to BF8
Publication Date: 2025.07.22 INTEL CORP
  • US12367045B2 patent drawing
  • US12367045B2 patent drawing
  • US12367045B2 patent drawing

AI summary

Techniques for converting FP16 data elements to BF8 data elements using a single instruction are described. An exemplary apparatus includes decoder circuitry to decode a single instruction, the single instruction to include a one or more fields to identify a source operand, one or more fields to identify a destination operand, and one or more fields for an opcode, the opcode to indicate that execution circuitry is to convert packed half-precision floating-point data from the identified source to packed bfloat8 data and store the packed bfloat8 data into corresponding data element positions of the identified destination operand; and execution circuitry to execute the decoded instruction according to the opcode to convert packed half-precision floating-point data from the identified source to packed bfloat8 data and store the packed bfloat8 data into corresponding data element positions.