FP4 Neural Network Training With Binary Shifters
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Solution Overview
Problem
Training neural networks is computationally expensive, and existing low precision domains like 8-bit floating point (FP8) do not fully address the efficiency needs, particularly in terms of computational cost and energy consumption.
Innovation Solution
Implementing a 4-bit training method using a novel floating-point format (FP4) with radix 4 and no mantissa bits, combined with binary shifters and adder trees to perform multiplication and addition without digital multiplier circuits, minimizing quantization errors through techniques like stochastic rounding and even/odd phase handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional high-precision floating point (FP32) is used for neural network training, then computational accuracy is maintained, but computational expense and energy consumption increase significantly
Solution Approach 1:
The patent changes the precision parameter from FP32 to FP4 (4-bit floating point), reducing the number of bits used to represent floating-point numbers. This parameter change directly reduces computational expense and energy consumption while maintaining acceptable training accuracy through careful design of the FP4 format and rounding strategies.
Solution Approach 2:
The patent employs stochastic rounding in the FP4 format, which introduces controlled randomness during quantization. This approach uses simpler, less precise representations (cheap objects) that can be discarded and re-sampled, achieving acceptable accuracy without the overhead of maintaining high precision throughout computation.
2Use of energy by moving object
If 8-bit floating point (FP8) is used to reduce computational expense, then energy consumption decreases, but it does not fully address efficiency needs
Solution Approach 1:
The patent advances the precision reduction from FP8 to FP4, further reducing the bit-width parameter. This more aggressive parameter change achieves greater energy savings and computational efficiency by using only 4 bits per floating-point number, with three bits for exponent and one bit for mantissa, compared to FP8's 8 bits.
Solution Approach 2:
The patent introduces dynamic rounding strategies (stochastic rounding, even/odd phase handling) that adapt during training. These dynamic approaches allow the system to maintain computational efficiency while adjusting precision characteristics on-the-fly to meet accuracy requirements, overcoming the static limitations of fixed-precision formats like FP8.
3Area of stationary object
If binary shifters and adder trees are used instead of digital multiplier circuits, then chip area decreases, but implementation complexity increases
Solution Approach 1:
The patent substitutes digital multiplier circuits with a combination of binary shifters and adder trees. This replacement uses simpler, more area-efficient components (shifters and adders) to achieve the same multiplication function, significantly reducing chip area at the cost of increased logic depth and implementation complexity.
Solution Approach 2:
The patent segments the multiplication operation into multiple simpler steps using binary shifters. Instead of a single complex multiplier circuit, the computation is divided into shifting operations followed by addition, breaking down the complex function into manageable, area-efficient segments that can be implemented with simpler logic.
4Power
If 4-bit precision is used to maximize energy efficiency, then power consumption reduces by 4-7 times, but quantization errors increase
Solution Approach 1:
The patent employs stochastic rounding and even/odd phase handling that introduce controlled randomness and phase alternation during quantization. These feedback mechanisms help distribute quantization errors more evenly and prevent systematic biases, maintaining training accuracy despite the aggressive 4-bit precision reduction and achieving 4-7 times power efficiency improvement.
Data Source
AI summary
An apparatus includes a floating-point gradient register; an integer register; a memory bank; and an array of processing units. Each of the units includes a plurality of binary shifters having an integer input configured to obtain corresponding bits of a 4-bit integer multiplicand, and a shift-specifying input configured to obtain corresponding bits in an exponent field of a 4-bit floating point multiplier. The multiplier is specified in a mantissaless four-bit floating point format including a sign bit, three exponent bits, and no mantissa bits. An adder tree has a plurality of inputs coupled to outputs of the plurality of shifters, and a rounder has an input coupled to an output of the adder tree. The integer inputs are connected to the integer register; the shift-specifying inputs are connected to the floating-point gradient register; and outputs of the rounders are coupled to the memory bank.