Emulating FP64 Matrix Multiplication via Low-Mantissa Segmentation
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Solution Overview
Problem
Current processor architectures require significant circuitry and time to perform matrix multiplication operations involving double-precision floating-point values, leading to inefficiencies and power constraints.
Innovation Solution
The technique involves dividing double-precision floating-point values into lower precision types, multiplying these values, and summing the products to achieve matrix multiplication, thereby reducing the hardware resources and time required for the operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If double-precision floating-point matrix multiplication is performed using conventional processor architectures, then calculation accuracy is maintained, but hardware resources and processing time increase significantly
Solution Approach 1:
The patent segments double-precision floating-point numbers into multiple lower-precision components (e.g., splitting a 64-bit FP64 number into two 32-bit FP32 numbers). This segmentation allows the system to perform matrix multiplication using simpler, less resource-intensive FP32 arithmetic while reconstructing the FP64 result, thereby reducing hardware requirements while maintaining accuracy.
Solution Approach 2:
The patent merges multiple lower-precision calculations to achieve the result of a single high-precision operation. By combining the results of multiple FP32 matrix multiplications and additions, the system emulates FP64 precision without requiring dedicated FP64 hardware, thus reducing device complexity while preserving measurement precision.
2Measurement precision
If double-precision floating-point matrix multiplication is performed using conventional processor architectures, then calculation accuracy is maintained, but processing time increases
Solution Approach 1:
The patent segments the high-precision multiplication operation into multiple parallel low-precision operations. By dividing the FP64 multiplication into multiple FP32 operations that can execute in parallel, the system reduces the sequential processing time while maintaining the final FP64 accuracy through proper combination of results.
Solution Approach 2:
The patent performs partial actions by computing only the necessary lower-precision components needed to reconstruct the full precision result. This partial computation approach avoids the need for complete FP64 hardware operations, reducing processing time while maintaining sufficient accuracy for the application.
3Measurement precision
If conventional processor architectures are used for matrix multiplication, then standard precision is achieved, but power consumption increases
Solution Approach 1:
The patent segments the high-power FP64 multiplication operation into multiple lower-power FP32 operations. Since FP32 arithmetic requires less hardware resources and operates at lower power consumption levels, performing multiple FP32 operations in parallel replaces the need for a single high-power FP64 operation, thereby reducing overall power consumption while maintaining standard precision.
Solution Approach 2:
The patent changes the precision parameter from FP64 to FP32 for the intermediate calculations. This parameter change enables the use of less power-intensive arithmetic units while the final result is reconstructed to FP64 precision, achieving a balance between power consumption and measurement precision.
Data Source
AI summary
The present disclosure relates to an apparatus that includes decoding circuitry that decodes a single instruction. The single instruction includes an identifier of a first source operand, an identifier of a second source operand, an identifier of a destination, and an opcode indicative of execution circuitry is to multiply from the identified first source operand and the identified second source operand and store a result in the identified destination. Additionally, the apparatus includes execution circuitry to execute the single decoded instruction to calculate a dot product by calculating a plurality of products using data elements of the identified first and second operands using values less precise than the identified first and second source operands, summing the calculated products, and storing the summed products in the destination.