FP8 Scale and Reduce Instructions for Neural Network Precision

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Solution Overview

Problem

Current machine learning and artificial intelligence applications face challenges in efficiently processing deep neural networks due to the high computational intensity and memory bandwidth issues associated with traditional floating-point arithmetic, particularly in converting higher-precision outputs to lower-precision formats like FP8 for matrix operations, which often require stochastic rounding to maintain accuracy and performance.

Innovation Solution

The introduction of instructions for calculating, extracting, and rounding FP8 data elements using specific hardware and software mechanisms that support FP8 formats, such as BF8 and HF8, which allow for variable exponent bias, stochastic rounding, and efficient memory utilization by converting higher-precision outputs to FP8, thereby alleviating memory and bandwidth constraints.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If traditional floating-point arithmetic (FP32, FP64) is used for deep neural network training, then numerical accuracy is maintained, but computational intensity and memory bandwidth requirements increase significantly

Engineering Contradiction:
Improvenumerical accuracyVSAvoidcomputational intensity
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent changes the precision parameter of floating-point arithmetic from traditional FP32/FP64 to lower-precision formats (FP8, BF8, HF8). This parameter change reduces the computational intensity and memory bandwidth requirements while maintaining adequate numerical accuracy for machine learning applications through specialized instructions for scale calculation, reduction, and stochastic rounding

Inventive Principle:
Principle #35Parameter changes

2Productivity

If lower-precision formats (FP8) are used to reduce memory pressure, then memory bandwidth requirements decrease, but numerical accuracy and convergence may deteriorate

Engineering Contradiction:
Improvememory bandwidth efficiencyVSAvoidnumerical accuracy
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The patent implements feedback mechanisms through scale calculation instructions that dynamically adjust the scaling factors based on the actual data distribution. This feedback loop allows the system to maintain numerical accuracy by adapting the precision parameters to the specific characteristics of the machine learning workload, ensuring convergence even with lower-precision formats

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent performs preliminary actions by calculating scale factors and performing stochastic rounding before the main computational operations. This preliminary processing prepares the data in a way that preserves numerical accuracy characteristics, enabling lower-precision formats to maintain convergence properties during subsequent computations

Inventive Principle:
Principle #10Preliminary action

3Quantity of substance

If higher-precision outputs are converted to lower-precision formats, then memory utilization improves, but conversion complexity and potential accuracy loss increase

Engineering Contradiction:
Improvememory utilizationVSAvoidconversion complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent segments the conversion process into distinct, specialized instructions: scale calculation to determine appropriate scaling factors, reduction operations to convert between precision formats, and stochastic rounding to maintain accuracy characteristics. This segmentation breaks down the complex conversion process into manageable, optimized steps that reduce overall conversion complexity

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20240045682A18-bit floating point scale and/or reduce instructions
Publication Date: 2024.02.08 INTEL CORP
  • US20240045682A1 patent drawing
  • US20240045682A1 patent drawing
  • US20240045682A1 patent drawing

AI summary

Techniques for scale and reduction of FP8 data elements are described. An exemplary instruction includes fields for an having fields for an opcode, an identification of a location of a first packed data source operand, an identification of a location of a second packed data source operand, and an identification of a packed data destination operand, wherein the opcode is to indicate that execution circuitry is to perform, for each data element position of the packed data source operands, a floating point scale operation of a FP8 data element of the first packed data source by multiplying the data element by a power of 2 value, wherein a value of the exponent of the power of 2 value is a floor value of a FP8 data element of the second packed data source, and store a result of the floating point scale operation into a corresponding data element position of the packed data destination operand.