Flat Panel Display Gate Electrode Overlap for Parasitic Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As the resolution of flat panel displays increases, parasitic capacitance between thin film transistors (TFTs) and wiring lines leads to distorted voltages and signals, causing deterioration in picture quality due to non-uniform distances and kick back phenomena.
Innovation Solution
The solution involves forming a gate electrode that extends over the adjacent wiring line, creating uniform capacitance by overlapping the gate electrode and wiring line, which helps minimize voltage changes and maintain uniform brightness across pixels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the distance among TFTs, capacitors, and wiring lines is reduced to increase resolution, then the resolution of the display is improved, but parasitic capacitance is generated between TFTs and wiring lines causing picture quality deterioration
Solution Approach 1:
The harmful insulating layer between the TFT and wiring line is removed in specific regions where the gate electrode extends over the wiring line. This extraction of the insulating layer eliminates the source of parasitic capacitance while maintaining necessary insulation elsewhere through the remaining insulating layers.
Solution Approach 2:
The gate electrode is extended in the vertical dimension to overlap the wiring line, creating a capacitive coupling that compensates for the harmful parasitic capacitance. This dimensional change allows the gate electrode to serve dual purposes: controlling the TFT and compensating for signal distortion.
2Reliability
If an insulating layer is formed between TFT and wiring line for insulation, then electrical insulation is achieved, but parasitic capacitance is generated causing voltage distortion
Solution Approach 1:
The insulating layer is selectively removed only in the region where the gate electrode overlaps the wiring line, while maintaining insulation in other critical regions. This local modification eliminates parasitic capacitance where harmful while preserving electrical insulation where necessary.
Solution Approach 2:
The gate electrode is extended to create a controlled capacitance with the wiring line that compensates for the harmful parasitic capacitance effects. By intentionally creating this capacitive coupling, the design converts a potential harm into a beneficial compensation mechanism that reduces kickback phenomena.
3Object-affected harmful factors
If gate electrode is extended to top of wiring line to create uniform capacitance, then picture quality is improved by minimizing kick back phenomenon, but device complexity increases
Solution Approach 1:
The gate electrode is designed to perform multiple functions: controlling the TFT channel and simultaneously creating a compensating capacitance with the wiring line. This multi-functionality is achieved by extending the gate electrode to overlap the wiring line, eliminating the need for separate compensation structures.
Solution Approach 2:
The gate electrode structure is merged with the wiring line area, creating a unified design where the gate electrode extends continuously over both the semiconductor layer and the wiring line. This merging simplifies the overall device structure by combining multiple functions into a single element.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents picture quality deterioration by ensuring uniform capacitance and minimizing the kick back phenomenon, allowing all pixels to emit light with consistent brightness.
Implementation Method 1
capacitance is formed by the gate electrode and the wiring line that overlap each other
Data Source
AI summary
In a flat panel display (FPD) and a method of manufacturing the same, the FPD includes a substrate, a semiconductor layer formed on the substrate, a wiring line formed on the substrate so as to be separated from the semiconductor layer, an insulating layer formed on the semiconductor layer and the wiring line, a gate electrode formed on the insulating layer formed on the semiconductor layer and extended to a top of the wiring line, and a source electrode and a drain electrode coupled to a source region and a drain region, respectively, of the semiconductor layer. Capacitance is formed by the gate electrode and the wiring line.