FPGA Heterogeneous Acceleration Card Protocol Processing Bypass
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Solution Overview
Problem
Current heterogeneous acceleration methods require server-powered protocol processing and forwarding, leading to high transmission delays and server dependence, making them inconvenient and inefficient for AI applications.
Innovation Solution
A method and system that analyze data packets to identify the data source end, customize or read a data message format from a configuration table, and perform acceleration processing directly on the FPGA heterogeneous acceleration card, bypassing server protocol processing and enabling direct communication between the host and the FPGA card.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data passes through server protocol processing and forwarding, then the system maintains centralized control, but transmission delay increases and server dependence strengthens
Solution Approach 1:
The patent extracts the protocol processing and forwarding functions from the server to the FPGA acceleration card. The FPGA card directly receives data packets from the host, performs protocol processing locally, and returns results without server intervention, thereby reducing transmission delay while maintaining system control through standardized interfaces
Solution Approach 2:
The patent introduces a direct communication channel between the host and FPGA acceleration card that bypasses the server as an intermediary. This direct path eliminates the server's protocol processing and forwarding steps, reducing transmission delay while the server retains system management capabilities
2Ease of manufacture
If hardware cards are plugged and unplugged through PCIE slots, then hardware deployment is possible, but the server must be powered down causing deployment inconvenience
Solution Approach 1:
The patent implements hot-plug capability that allows FPGA acceleration cards to be installed and removed while the server remains powered on. This preliminary preparation of the hardware interface enables deployment actions to be taken in advance without requiring system shutdown, improving deployment convenience
Solution Approach 2:
The patent enables dynamic addition and removal of FPGA acceleration cards during server operation. The system dynamically adapts to hardware changes without requiring power cycles, allowing flexible deployment and reconfiguration of acceleration resources while the server continues to run
3Device complexity
If the server processes all data packets through protocol conversion and forwarding, then centralized management is maintained, but processing efficiency decreases
Solution Approach 1:
The patent segments the data processing function by separating protocol processing from acceleration processing. The FPGA acceleration card handles protocol processing and data acceleration independently, while the server maintains centralized management through configuration and monitoring, thereby improving processing efficiency without losing management control
Solution Approach 2:
The patent enables the FPGA acceleration card to autonomously handle protocol processing and data acceleration without requiring server intervention for each data packet. The card independently receives packets from the host, processes them according to its configured function, and returns results directly, significantly improving processing efficiency while the server maintains overall system management
Data Source
AI summary
A heterogeneous acceleration method, including the following steps: analyzing a received target data packet to obtain data source end identification information; when the data source end identification information does not exist in a configuration information table, customizing a data message format according to the target data packet to obtain a target data message format, or when the data source end identification information exists in the configuration information table, reading the target data message format from the configuration information table; and according to the target data message format, performing acceleration processing on the target data packet to obtain processed data, and returning the processed data to a data source end.