Dynamic Power Budget Controller for FPGA Accelerator Reconfiguration
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Solution Overview
Problem
In computationally intense environments like big-data and cloud computing, existing systems face challenges in increasing performance while keeping power consumption within acceptable limits, as they often require rebooting and reloading of executable code for configuration changes, leading to inefficiencies in power management and performance optimization.
Innovation Solution
The implementation of a dynamically reconfigurable accelerator that includes a specially purposed semiconductor chip and a general purpose processor, managed by a controller that dynamically adjusts power allocations and configurations to optimize performance and power consumption without rebooting the general purpose processor, by using pre-stored images and power profiles for different acceleration tasks and switching between them seamlessly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If configuration changes are made to the accelerator, then performance optimization is achieved, but the system requires rebooting and reloading of executable code which causes loss of time and reduces productivity
Solution Approach 1:
The patent implements dynamic reconfiguration of the accelerator by allowing the controller to modify configuration parameters and swap bitstream images during runtime without requiring a system reboot. The controller can load new configuration images from memory and apply them to the FPGAs dynamically, enabling the accelerator to adapt to different computational tasks while maintaining continuous operation of the host system.
Solution Approach 2:
The system pre-loads multiple configuration images and power profiles into memory before they are needed. When a configuration change is required, the controller can immediately switch to a pre-loaded image without requiring external storage access or system reboot, significantly reducing the time penalty associated with configuration changes.
2Use of energy by moving object
If power consumption is reduced, then energy efficiency is improved, but performance may be compromised
Solution Approach 1:
The controller dynamically adjusts power consumption by selecting from multiple pre-defined power profiles that correspond to different operational modes. Each power profile contains optimized configuration parameters that balance power consumption and performance based on the current computational workload. The controller can switch between profiles to match varying performance requirements while optimizing energy efficiency.
Solution Approach 2:
The system applies partial reconfiguration techniques where only specific portions of the accelerator are reconfigured or activated based on the current task requirements. This allows the system to reduce power consumption by deactivating unused functional units while maintaining necessary computational capabilities, rather than operating at full power continuously.
3Adaptability or versatility
If the accelerator dynamically reconfigures during runtime, then adaptability is improved, but device complexity increases
Solution Approach 1:
The controller is designed as a universal management unit that handles multiple functions including configuration image loading, power profile management, runtime reconfiguration, and performance monitoring. By consolidating these diverse functions into a single multi-functional controller, the system manages complexity through functional integration rather than proliferation of separate control mechanisms.
Solution Approach 2:
The controller acts as an intermediary layer between the host processor and the FPGAs, managing all configuration changes and power adjustments. This intermediary absorbs the complexity of dynamic reconfiguration management, shielding the host system from complex low-level operations while enabling sophisticated accelerator optimization through standardized control interfaces.
Data Source
AI summary
An apparatus is described. The apparatus includes an accelerator having an interface to plug into an electronic system. The accelerator includes a field programmable gate array integrated circuit to perform acceleration, a general purpose processor integrated circuit to execute software related to the acceleration and controller circuitry to dynamically change, without rebooting the general purpose processor integrated circuit, allocation of the accelerator's power budget to the field programmable gate array integrated circuit and the general purpose processor integrated circuit.