FPGA Access Chip for Intelligent Substation Message Processing
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Solution Overview
Problem
In intelligent substations, the real-time processing and transmission of numerous messages are inefficient, leading to low message transmission efficiency and impacting operational efficiency.
Innovation Solution
The implementation of an intelligent power server with an FPGA access chip and an embedded high-bandwidth switched communication network, allowing direct access of merging units and intelligent terminal devices to transport ports, enabling real-time data collection and processing, and using a real-time business CPU to manage message reception and transmission through reception and transmission buffers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple protection apparatuses are deployed in each bay to cover different device types, then protection coverage is improved, but message quantity increases and transmission efficiency deteriorates
Solution Approach 1:
The patent segments the substation into multiple bays, with each bay having dedicated protection apparatuses for specific device types. This spatial and functional segmentation allows parallel processing of messages from different bays, improving overall transmission efficiency while maintaining comprehensive protection coverage through distributed protection units.
Solution Approach 2:
The patent introduces a message gateway as an intermediary component that receives, filters, and forwards messages between protection apparatuses and other substation systems. This intermediary optimizes message routing, reduces unnecessary transmissions, and improves overall message transmission efficiency without compromising protection coverage.
2Device complexity
If traditional message processing architecture is used, then system complexity is reduced, but real-time processing capability deteriorates
Solution Approach 1:
The patent replaces traditional CPU-based message processing with FPGA-based hardware acceleration. The FPGA implements dedicated message processing circuits that operate in parallel, significantly reducing processing delays while maintaining manageable system complexity through standardized hardware modules.
Solution Approach 2:
The patent pre-configures message processing rules and routing tables in the FPGA before operation. Messages are processed according to pre-established logic paths, eliminating the need for complex runtime decision-making and reducing processing delays without increasing operational system complexity.
3Ease of manufacture
If CPU-based message processing is used, then implementation simplicity is improved, but processing load and delays increase
Solution Approach 1:
The patent substitutes CPU software-based message processing with FPGA hardware-based processing. The FPGA implements dedicated logic circuits for message parsing, filtering, and forwarding, achieving parallel processing that dramatically improves message processing speed while maintaining implementation simplicity through standardized hardware designs.
Solution Approach 2:
The patent implements dynamic message processing in the FPGA where processing priorities and routing paths can be adjusted based on message types and system conditions. This dynamic capability allows the system to handle varying message loads efficiently without requiring complex CPU intervention, improving processing speed while keeping the system relatively simple.
Data Source
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Figure 3
AI summary
The disclosure relates to a data transferring method based on a protection and control system for an intelligent substation. Merging unit and intelligent terminal integrated devices for all bays in an intelligent substation are respectively accessed to corresponding transport ports of an FPGA access chip of an intelligent power server. The method includes: in a reception period, messages are read from a reception buffer clip by a real-time business central processor, subjected to a process and then written into the reception buffer clip; in a transmission period, the real-time business central processor issues indication information to the FPGA access chip, causing the chip to generate messages according to the indication information and write the messages into a transmission buffer.