FPGA Activation Mode Control for Image Processing
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Solution Overview
Problem
Conventional image forming apparatuses require significant hardware resources and increased costs due to the need for a dedicated setting circuit to manage activation conditions for the CPU, and they struggle with remote maintenance and ensuring proper operation according to set conditions.
Innovation Solution
An image processing apparatus utilizing an integrated circuit element with memory, such as an FPGA, that sets and manages the activation condition of the controller based on information written in the memory, allowing it to function efficiently and adapt to external information sources, thereby eliminating the need for a dedicated setting circuit and enabling remote maintenance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dedicated setting circuit is used to manage CPU activation conditions, then the activation condition can be controlled accurately, but the hardware resources increase and cost rises
Solution Approach 1:
The patent applies multi-functionality by enabling the CPU itself to perform the setting function that was previously dedicated to a separate setting circuit. The CPU uses its own resources (register, instruction cycle) to read activation condition data from ROM and control its activation, thereby eliminating the need for a dedicated setting circuit while maintaining accurate activation condition control.
2Ease of operation
If programs or data are collectively managed in the main body, then unit management is simplified, but the memory capacity requirement increases considerably
Solution Approach 1:
The patent extracts the activation condition data from the main body memory and places it in a separate ROM (read-only memory) located in the power supply unit. This extraction allows the main body to manage only essential data while the ROM stores the activation condition information, thereby reducing the memory capacity requirement in the main body while maintaining simplified management through centralized storage.
3Adaptability or versatility
If the apparatus is located in a distant place, then installation flexibility is improved, but maintenance becomes difficult
Solution Approach 1:
The patent implements self-service by enabling the CPU to automatically detect its activation status and self-diagnose activation condition failures. When an activation condition error occurs, the CPU automatically reads correction data from ROM and corrects itself without requiring external intervention or physical access, thereby maintaining ease of maintenance even when the apparatus is located remotely.
Data Source
AI summary
An FPGA functions as an activation mode setting circuit for loading activation data stored on a PROM into a circuit setting memory and setting an activation mode when activating the CPU. The FPGA outputs an activation mode setting signal to the CPU, and the CPU is activated in the set activation mode. After the CPU is activated, it follows predetermined processing steps, and performs a control operation to load the circuit setting data stored in a storage section into the circuit setting memory. Thus, the FPGA is constructed as a circuit having a desired function, and also constructed as an activation mode setting circuit when activating the CPU.