FPGA Logic Module with Versatile Adder for Fast Carry Propagation

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Solution Overview

Problem

Existing adder circuits in field-programmable gate arrays (FPGAs) face inefficiencies in terms of added circuitry, power consumption, and delay, particularly in implementing arithmetic functions due to reliance on dedicated XOR gates and substantial delay in carry propagation.

Innovation Solution

A logic module for FPGAs is designed using an N-level tree of 2:1 multiplexers, allowing internal signal tapping and replacing XOR gates with multiplexers, which reduces hardware requirements and enhances flexibility by enabling programmable inversion of inputs and carry propagation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If dedicated XOR gates are used for adder circuits, then arithmetic function implementation is enabled, but hardware complexity and power consumption increase

Engineering Contradiction:

Improvearithmetic function implementationVSAvoidhardware complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent makes the LUT serve multiple functions by using its output to drive both the sum calculation (via XOR with carry-in) and the carry-out generation. The same LUT that implements the boolean function also provides inputs to the carry chain, eliminating the need for dedicated arithmetic hardware and reducing overall device complexity while maintaining arithmetic functionality

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges the function of dedicated XOR gates and carry look-ahead logic into the existing LUT structure. By tapping internal LUT signals to drive carry chain inputs and using the LUT output with carry-in in an XOR operation, the design combines multiple arithmetic functions into a single integrated structure, reducing hardware complexity

Inventive Principle:

Principle #5Merging (Combining)

2Productivity

If traditional carry chain structures are used, then arithmetic operations are supported, but carry propagation delay increases

Engineering Contradiction:

Improvearithmetic operation supportVSAvoidcarry propagation delay

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The patent applies carry look-ahead techniques by pre-computing carry signals using tapped LUT outputs before they are needed for the final sum calculation. The carry chain is driven by signals from intermediate LUT stages, allowing carry propagation to occur in parallel with other logic operations, thereby reducing the critical path delay

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent segments the carry propagation path by using multiple tap points from different LUT stages to drive different carry chain inputs. This breaks down the long carry propagation path into shorter segments, allowing faster carry signal generation and reducing overall propagation delay

Inventive Principle:

Principle #1Segmentation

3Adaptability or versatility

If additional circuitry is added for arithmetic functions, then arithmetic capabilities are enhanced, but power consumption increases

Engineering Contradiction:

Improvearithmetic capabilitiesVSAvoidpower consumption

Core Design Contradiction:

Adaptability or versatilityVSUse of energy by stationary object

Solution Approach 1:

The patent enables arithmetic capabilities by making the LUT multi-functional, using its output to drive both normal logic operations and arithmetic operations (sum and carry). This eliminates the need for separate dedicated arithmetic circuitry that would consume additional power, as the same LUT infrastructure serves both purposes

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The LUT serves itself by providing its own internal signals to drive the carry chain and arithmetic operations. The tapped LUT outputs are reused to generate carry signals without requiring external or additional dedicated arithmetic logic, thereby reducing power consumption while maintaining enhanced arithmetic capabilities

Inventive Principle:

Principle #25Self-service

4Adaptability or versatility

If flexible LUT configuration is used, then programming capability is enhanced, but carry propagation speed may be reduced

Engineering Contradiction:

Improveprogramming capabilityVSAvoidcarry propagation speed

Core Design Contradiction:

Adaptability or versatilityVSSpeed

Solution Approach 1:

The patent maintains fast carry propagation by pre-positioning carry input signals from tapped LUT outputs before the configurable logic stage. Even though the LUT is programmable, the carry chain is driven by these pre-computed signals, allowing the configurable logic to be programmed for different functions without impacting the speed of carry propagation

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS8085064B2Logic module including versatile adder for FPGA

Publication Date: 2011.12.27 MICROSEMI SOC CORP

AI summary

A logic module for an FPGA includes a LUT formed from an N-level tree of 2:1 multiplexers. Each of the N inputs to the LUT is connected to the select inputs of the multiplexers in one level of the tree. Each of the data inputs at the leaves of the tree is driven by a configuration memory cell that produces either a logic 0 or a logic 1. The output of the single multiplexer at the last level of the tree forms a Y output and is coupled to one input of an XOR gate and to the select input of a two-input carry multiplexer. The 0 input of the carry multiplexer is coupled to a G input. A CI input is coupled to the other input of the XOR gate and to the 1 input of the carry multiplexer.