FPGA Allocation Map Signal Value Calculation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In real-time simulation of complex, dynamic models, especially in automotive hardware-in-the-loop simulations, existing methods struggle to meet tight time constraints and low latencies, particularly with CPU-based simulations, which are inadequate for fast control loops and dynamic systems like in-cylinder pressure sensors and electric motors.
Innovation Solution
A method for generating an allocation map based on FPGA source code, where signals and registers are mapped, allowing for the determination of signal values at runtime using calculation rules, thereby omitting the need to read out specific registers directly, reducing time and resource requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If all registers are read out directly from the FPGA, then complete signal data is obtained, but time and resource requirements increase
Solution Approach 1:
The patent extracts only the essential primary signal values from FPGA registers that are needed for control decisions, while deriving secondary signal values through calculation. This selective extraction approach obtains the necessary measurement data without the time penalty of reading all registers, directly resolving the contradiction between complete data acquisition and time efficiency.
Solution Approach 2:
The patent performs preliminary identification of calculation relationships between signals during the allocation map generation phase. By pre-determining which signal values can be derived from others through mathematical relationships, the system prepares the optimization strategy in advance, enabling efficient readout without compromising measurement completeness.
2Ease of operation
If more registers are mapped to signals, then signal values can be read out directly, but device complexity and resource usage increase
Solution Approach 1:
The patent makes the allocation map generation tool universal by automatically handling the complex task of identifying calculation relationships and generating optimized readout strategies. This multi-functional tool performs both the analysis of signal relationships and the generation of allocation maps, simplifying the user's operation while managing the underlying complexity automatically.
Solution Approach 2:
The system performs self-service by automatically analyzing the FPGA source code, identifying calculation relationships between signals, and generating the allocation map without manual intervention. This self-organizing process reduces device complexity from the user's perspective while maintaining optimal signal reading capabilities.
3Adaptability or versatility
If CPU-based simulation is used, then flexibility is maintained, but real-time performance and response time are insufficient
Solution Approach 1:
The patent introduces an allocation map as an intermediary layer between the FPGA hardware acceleration and the control software. This allocation map efficiently maps signal values from FPGA registers to software variables, enabling the system to maintain CPU-based simulation flexibility while achieving real-time performance through optimized data access patterns that reduce overhead.
Solution Approach 2:
The patent segments the simulation system into distinct functional components: FPGA-based dynamic model computation for time-critical calculations, and CPU-based control logic for higher-level decision-making. This segmentation allows each component to operate in its optimal performance regime, with the FPGA handling speed-critical operations and the CPU maintaining flexibility for adaptive control strategies.
Data Source
AI summary
A method for creating an allocation map, wherein the allocation map is created based on an FPGA source code, wherein the source code uses at least a first signal at a first location, wherein at least a first register is mapped to the first signal, wherein in the allocation map, the first signal and the first register are listed as mapped to one another, wherein a second signal is used at a second location in the FPGA source code, wherein it is automatically detected that the value of the second signal can be determined from the value of the first signal according to a first calculation rule, wherein in the allocation map, the second signal, the first register and the first calculation rule are listed as mapped to one another.