FPGA Arithmetic Circuit Diversity for Common-Factor Error Checking
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Solution Overview
Problem
Conventional error verification methods in programmable logic devices, such as FPGAs, fail to detect errors caused by common factors like temperature, voltage, and clock fluctuations due to redundant arithmetic operation circuits producing the same results even when errors occur, resulting in a low error detection rate.
Innovation Solution
A programmable logic device and method that form multiple arithmetic operation circuits with different combinations and connection states of circuit blocks, allowing for error verification by comparing their outputs to improve detection rates, utilizing a verification circuit to determine error occurrence based on non-coincident results.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundant arithmetic operation circuits with the same circuit block combination are used for error verification, then the verification method is simple to implement, but the error detection rate is low because common factors cause identical errors in all circuits
Solution Approach 1:
The patent applies local quality by making each arithmetic operation circuit have a different combination of circuit blocks (e.g., different numbers of NAND gates, NOR gates, inverters) while maintaining the same overall arithmetic function. This local variation in circuit structure ensures that common factors affect each circuit differently, enabling error detection through result comparison.
Solution Approach 2:
The patent changes the parameters of circuit block combinations (such as the number of logic gates, their arrangement, and connection states) across different arithmetic operation circuits. By varying these structural parameters while keeping the arithmetic function constant, the circuits respond differently to common factors, thereby improving error detection capability.
2Adaptability or versatility
If the number of circuit blocks is increased to perform more arithmetic operations, then the arithmetic operation functions are enhanced, but the probability of malfunction due to charged particles increases
Solution Approach 1:
The patent creates multiple copies of arithmetic operation circuits that perform the same function but with different internal circuit block combinations. These copied circuits are subjected to the same input and environmental conditions, allowing error detection through comparison while maintaining the required arithmetic operation capabilities.
Solution Approach 2:
The patent implements error verification by comparing results from multiple differently-configured circuits before accepting the output. This beforehand cushioning mechanism detects errors caused by charged particles or common factors before they propagate, protecting the system's reliability despite having many circuit blocks.
Data Source
AI summary
Arithmetic operation circuits and a verification circuit are formed by loading configuration information into a configuration memory in an FPGA. Arithmetic operation circuits have the same arithmetic operation function, but are different from each other in combination of the circuit blocks. The arithmetic operation circuits are formed by combining the circuit blocks to make the maximum use of the DSP block, while the arithmetic operation circuit is formed by combining the circuit blocks other than DSP block. The arithmetic operation circuits each are configured to use a block RAM as the data hold memory, while the arithmetic operation circuit is configured to use a distributed RAM as the data hold memory. Each of the arithmetic operation circuits receives the input data, and outputs arithmetic operation result data (V1 to V3). A verification circuit compares the arithmetic operation result data to verify whether errors occur.