Reconfigurable FPGA Arithmetic Circuits for Resource-Constrained DSP
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Solution Overview
Problem
Current field-programmable gate arrays (FPGAs) face inefficiencies in performing arithmetic operations due to fixed and non-programmable embedded multipliers, which limit flexibility and resource utilization in computationally intensive tasks like digital signal processing and image processing.
Innovation Solution
The implementation of programmable logic circuits and lookup tables (LUTs) to create flexible adder and multiplier structures, such as two-operand adders and multipliers, that can be configured to perform radix-4 modified-Booth multiplication and other arithmetic operations, reducing resource usage and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If fixed embedded multipliers are used in FPGAs, then arithmetic operations can be performed, but flexibility and resource utilization are limited
Solution Approach 1:
The patent implements dynamic arithmetic circuits where the operation type (addition, multiplication, etc.) and operand widths can be configured and changed at runtime. The producer structure can dynamically select between different operations and the adder structure can adapt to different operand sizes, transforming static embedded multipliers into dynamic, reconfigurable arithmetic units that improve flexibility without proportionally increasing resource complexity
Solution Approach 2:
The patent creates universal arithmetic structures that can perform multiple operations. The producer structure generates partial products for both addition and multiplication operations, while the adder structure can handle different types of arithmetic operations. This multi-functionality allows a single reconfigurable structure to replace multiple dedicated circuits, improving adaptability while optimizing resource utilization
2Adaptability or versatility
If LUT-based adders and multipliers are implemented, then flexibility is improved, but resource usage increases
Solution Approach 1:
The patent merges the partial product generation and addition functions into a unified reconfigurable structure. The producer structure that generates partial products is directly integrated with the adder structure, allowing shared resources and reduced redundancy. This merging approach enables LUT-based implementation to achieve flexibility while optimizing resource usage by eliminating separate dedicated circuits for each function
Solution Approach 2:
The patent segments the arithmetic operation into distinct configurable stages: partial product generation in the producer structure and accumulation in the adder structure. Each stage can be independently configured and optimized, allowing fine-grained control over resource allocation. This segmentation enables efficient LUT utilization by assigning specific LUTs to specific functional stages based on operational requirements
3Productivity
If more processing resources are allocated to arithmetic operations, then processing speed improves, but resource availability for other tasks decreases
Solution Approach 1:
The patent implements dynamic resource allocation where the arithmetic circuits can be configured and activated based on instantaneous computational requirements. The reconfigurable producer and adder structures can be enabled or disabled, and their operational parameters adjusted, allowing processing resources to be dynamically allocated to arithmetic operations when needed and released for other tasks when not needed, thereby maintaining high processing speed while preserving resource availability
Data Source
AI summary
A two-operand adder circuit is provided. The two-operand adder circuit may be configured to receive a bit of a second addend, a carry-in bit, and one or more bits encoding a bit of a first addend, and to provide an output representing a sum of the bit of the first addend, the bit of the second addend, and the carry-in bit.