FPGA ARM I2C Data Transmission via Generated Address
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Solution Overview
Problem
Data transmission between ARM and FPGA processors of different architectures is inefficient due to the need for explicit address data transmission via the IIC bus, leading to increased data processing and transmission overhead.
Innovation Solution
A method and device that generate and use secondary address data for sequential content data, reducing the need for explicit address data transmission by incrementing address values accordingly, thereby optimizing data processing and transmission efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If address data is explicitly transmitted for each content data via IIC bus, then data can be accurately located and stored, but the amount of data to be transmitted increases, resulting in low transmission efficiency
Solution Approach 1:
The patent extracts and removes the address data from the transmission process. Instead of transmitting both address and content data through the IIC bus, only the content data is transmitted. The address information is generated locally at the receiving end based on the received content data, thereby eliminating the overhead of transmitting address data while maintaining accurate data location capability
Solution Approach 2:
The patent uses a hash function to generate a compact representation (hash value) of the original data as an address identifier. This hash value serves as a compressed copy of the address information, allowing the system to locate and retrieve data efficiently without transmitting the full address data through the bus
2Reliability
If address data is included with each content data in communication packets, then data can be correctly mapped to storage locations, but the communication data occupies larger space and requires more processing
Solution Approach 1:
The patent changes the parameter representation by transforming the address data from a direct numerical value transmitted through the bus into a hash value generated locally. This parameter transformation reduces the amount of data that needs to be transmitted and processed, while the hash function ensures that the mapping accuracy is maintained through its deterministic nature
3Reliability
If complete address and content data are transmitted for each data element, then data integrity is ensured, but the transmission time and processing overhead increase
Solution Approach 1:
The patent extracts the address information from the transmission stream, keeping only the essential content data for transmission. The address is reconstructed at the receiving end using a hash function applied to the received content data, thereby reducing transmission time while ensuring data integrity through the deterministic hash mapping
Solution Approach 2:
The patent performs preliminary hashing of the content data at the receiving end before data storage or retrieval operations. This preliminary action of generating the address from the content data ensures that the full address information is available immediately upon receipt, eliminating the need to wait for separate address transmission and reducing overall processing time
Data Source
AI summary
The present disclosure provides a data transmission method and device. The data transmission method is used for transmitting data between an advanced reduced instruction set computing machine (ARM) and a field programmable logic gate array (FPGA) via an Inter-Integrated Circuit (IIC) bus, comprising the following steps: receiving, by the FPGA, communication data transmitted by the ARM via the IIC bus, wherein the communication data comprises first address data, first content data and N second content data, N being an integer greater than 0, the first content data and the N second content data being arranged in sequence, and the first address data being address data corresponding to the first content data; and generating, by the FPGA, second address data corresponding to each of the second content data according to the sequence of the N second content data and the first address data.