Bridged FPGA-ASIC Circuit for Low-Latency Application Execution
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The complexity in ASIC design leads to potential errors and increased development costs, and since ASICs are not reprogrammable, redesigns are necessary for different applications, which can delay product shipments and increase costs. Additionally, integrating multiple components in ASICs is beneficial for applications with critical latency but not for individual operations, where performance can be improved by offloading functionalities to a bridge chip.
Innovation Solution
A system comprising a Field-Programmable Gate Array (FPGA) and an Application-Specific Integrated Circuit (ASIC) on the same circuit board, where the FPGA decodes instructions and transmits them to the ASIC for execution, allowing the ASIC to be swapped for different applications, and handles communications with external devices, reducing design complexity and costs while improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If ASIC integrates multiple components for critical latency applications, then performance is improved, but device complexity and design errors increase
Solution Approach 1:
The system divides functionality into two separate chips: an ASIC chip that handles computation-critical functions where latency matters, and an FPGA chip that handles communication and control functions. This segmentation allows each chip to be optimized for its specific purpose without the complexity of integrating all functions into a single ASIC.
Solution Approach 2:
The FPGA chip acts as an intermediary between external devices and the ASIC chip. It handles communication protocols, data formatting, and control operations, allowing the ASIC to focus purely on computation without the overhead of communication complexity.
2Manufacturing precision
If ASIC is designed for a specific application, then manufacturing precision is improved, but adaptability deteriorates requiring redesigns for different applications
Solution Approach 1:
The system makes the communication and control portion dynamic and reconfigurable through the FPGA chip, while keeping the computation-critical ASIC portion static and optimized. When application requirements change, only the FPGA needs to be reconfigured or replaced, not the entire ASIC design.
Solution Approach 2:
The FPGA chip provides universal functionality for handling various communication protocols and control operations across different applications. This allows the same ASIC chip to serve multiple applications by pairing it with different FPGA configurations.
3Device complexity
If all functionalities are integrated in ASIC, then device complexity is reduced, but ease of operation deteriorates requiring swapping entire chips for different applications
Solution Approach 1:
By segmenting the system into ASIC and FPGA components, the patent enables independent replacement of the FPGA chip while keeping the ASIC chip in place. This reduces the operational burden compared to swapping entire integrated systems.
Data Source
AI summary
Methods, systems, and apparatus, including a system that includes a first integrated circuit chip configured to store application logic for one or more executable applications; and a second integrated circuit chip communicatively coupled to the first integrated circuit chip, the second integrated circuit chip including an instruction decoder configured to decode instructions for executing the one or more executable applications; and a communication interface configured to transmit the decoded instructions to the first integrated circuit chip to execute the one or more executable applications on the first integrated circuit chip.