Bridged FPGA-ASIC Circuits for Flexible Deterministic Execution
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Solution Overview
Problem
The complexity in ASIC design leads to potential errors and increased development costs, and since ASICs are not reprogrammable, redesigns are necessary for different applications, which can delay product shipments and increase costs.
Innovation Solution
A system comprising a Field-Programmable Gate Array (FPGA) and an Application-Specific Integrated Circuit (ASIC) on the same circuit board, where the FPGA decodes instructions and transmits them to the ASIC for execution, allowing the ASIC to be swapped for different designs or applications, reducing design complexity and enabling deterministic execution of instructions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If ASIC design complexity is increased to handle more functions, then functionality is improved, but design errors and development costs increase
Solution Approach 1:
The system divides functionality into two separate chips: an FPGA chip that handles instruction decoding and a control chip that executes instructions. This segmentation allows each chip to be optimized for its specific function, reducing overall design complexity and errors while maintaining high functionality.
Solution Approach 2:
The patent introduces an intermediate instruction set architecture (ISA) layer that mediates between the FPGA's control logic and the ASIC's execution units. This intermediary abstraction layer simplifies the design by providing a standardized interface, reducing the complexity of direct integration and minimizing design errors.
2Productivity
If ASIC is designed for a specific application, then performance is improved, but redesign is necessary for different applications, increasing development costs and delaying shipments
Solution Approach 1:
The system employs a dynamic architecture where the FPGA chip can be reprogrammed with different instruction sets and the control chip can execute different applications by loading new instruction binaries. This dynamic reconfigurability allows the same hardware platform to adapt to different applications without physical redesign, maintaining high performance while enabling flexibility.
Solution Approach 2:
The patent creates a universal platform where the control chip can execute multiple different applications through a standardized instruction execution mechanism. The FPGA chip serves as a universal controller that can be configured for different applications, and the control chip provides universal instruction execution capabilities, allowing one hardware design to serve multiple applications.
3Device complexity
If all functions are integrated on one chip, then device complexity is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The system segments the integrated circuit into two separate chips: an FPGA chip for control functions and a control chip for execution functions. This segmentation reduces the complexity of each individual chip, making manufacturing more feasible with standard precision requirements, while still achieving the functionality of a highly integrated system through inter-chip communication.
Data Source
AI summary
Methods, systems, and apparatus, including a system that includes a first integrated circuit chip configured to store application logic for one or more executable applications; and a second integrated circuit chip communicatively coupled to the first integrated circuit chip, the second integrated circuit chip including an instruction decoder configured to decode instructions for executing the one or more executable applications; and a communication interface configured to transmit the decoded instructions to the first integrated circuit chip to execute the one or more executable applications on the first integrated circuit chip.