Asynchronous FPGA Controller Communication via Message Queues
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Solution Overview
Problem
High performance memory access devices require both high throughput data paths and flexible control paths, but existing technologies face challenges in integrating gate array devices with external processors due to latency issues and synchronous communication limitations.
Innovation Solution
Implementing asynchronous communication between external processors and gate array controllers using message submission and completion queues, which allows for high throughput and dynamic control by partitioning the data path and utilizing a 'push' data transfer mode to reduce latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If synchronous communication is used between external processor and gate array controller, then control reliability is improved, but communication latency increases and throughput decreases
Solution Approach 1:
The communication interface is segmented into separate message submission queues and completion queues, allowing independent operation of requests and responses. This segmentation enables the external processor to submit commands without waiting for immediate responses, reducing latency while maintaining control reliability through proper queue management and acknowledgment mechanisms.
Solution Approach 2:
Message queues serve as intermediaries between the external processor and gate array controller. The submission queue receives commands from the processor while the completion queue delivers responses back, decoupling the synchronous control dependency and enabling asynchronous operation that reduces communication latency without sacrificing reliability.
2Speed
If gate array device is used for high throughput data path, then data transfer speed is improved, but control flexibility decreases
Solution Approach 1:
The system segments control functions by using message queues to separate command submission from execution. The gate array device handles high-speed data transfer operations while the external processor maintains flexible control through the queue-based messaging system, allowing adaptive control decisions without compromising data transfer speed.
Solution Approach 2:
The message queue system introduces dynamic control capabilities to the gate array device. Commands can be submitted asynchronously and processed dynamically based on current system conditions, allowing the rigid gate array structure to adapt to varying control requirements while maintaining high throughput data path performance.
3Adaptability or versatility
If external processor is used for flexible control path, then control adaptability is improved, but data transfer latency increases
Solution Approach 1:
The external processor can submit control commands to the message submission queue in advance of actual data transfer operations. This preliminary action allows the gate array device to prepare for high-speed data transfer while the processor continues with other adaptive control tasks, reducing overall latency while maintaining control adaptability.
Solution Approach 2:
Message queues act as intermediaries that buffer control commands and responses between the external processor and gate array device. This intermediary mechanism allows the processor to maintain adaptive control logic without being bottlenecked by synchronous data transfer operations, reducing latency while preserving control flexibility.
4Measurement precision
If synchronous blocking events are used for communication, then control precision is improved, but system throughput decreases
Solution Approach 1:
The communication protocol is segmented into independent submission and completion queues, allowing precise control commands to be submitted without blocking the system. This segmentation enables the gate array device to process commands with precision while the external processor continues other operations, maintaining system throughput without sacrificing control precision.
Solution Approach 2:
The message queue system enables continuous submission of control commands without synchronous blocking. The external processor can continuously submit new commands to the submission queue while completion queues deliver responses asynchronously, maintaining both control precision and high system throughput through uninterrupted operation.
Data Source
AI summary
A request is received via a message submission queue. The request is sent from a core associated with an external processor coupled by a communication interface. The message submission queue is associated with a memory access engine circuit configured to perform one or more memory access functions. The memory access engine circuit is used to dequeuer a next message from its corresponding message submission queue. The memory access engine circuit is used to perform a message function invoked by the message. The memory access engine circuit is used to receive a result of performing the message function. The memory access engine circuit is used to prepare and send to an external processing core that sent the message a response message determined based at least in part on the result.