FPGA-Based ATE System for UFS Protocol Testing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional automated test equipment (ATE) systems are limited in testing multiple devices under test (DUTs) due to processing load on the tester processor and bandwidth constraints, and they lack native support for Universal Flash Storage (UFS) protocols, which restricts their ability to test UFS-compliant DUTs effectively.
Innovation Solution
The solution involves configuring off-the-shelf FPGAs to generate commands and data internally, using Serializer/Deserializer (SerDes) channels to communicate with UFS-compliant DUTs, and implementing a demultiplexer to route data through switchable input terminations for Unterminated Receive mode and power saving state detection, allowing for concurrent testing of multiple UFS-compliant DUTs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional ATE systems use tester processor to generate commands and test patterns, then the system can test DUTs, but the processing load on the tester processor increases and bandwidth constraints limit the number of DUTs that can be tested
Solution Approach 1:
The system divides the command and test pattern generation functionality from the tester processor and assigns it to individual FPGA devices. Each FPGA independently generates commands and test patterns for its associated DUT, eliminating the bottleneck where the tester processor had to generate all commands for all DUTs sequentially. This segmentation allows parallel operation of multiple FPGAs, thereby increasing the number of DUTs that can be tested simultaneously while reducing the processing load on the tester processor.
2Adaptability or versatility
If conventional ATE systems use fixed hardware bus adapter cards for specific protocols, then the system can test DUTs with that protocol, but the system lacks adaptability to test UFS-compliant DUTs without hardware replacement
Solution Approach 1:
The FPGA devices are configured to provide universal protocol support, including native support for UFS protocols. Instead of requiring separate hardware bus adapter cards for each protocol, the FPGAs can be programmed to handle multiple protocols (PCIe, USB, SATA, SAS, UFS, etc.), allowing the same hardware platform to test DUTs with different protocols by simply reconfiguring the FPGA logic rather than replacing physical hardware components.
3Speed
If SerDes channels are used for high-speed communication with UFS DUTs, then communication efficiency improves, but the system cannot support Unterminated Receive mode required by UFS low-speed gears
Solution Approach 1:
The system implements dynamic switching between terminated and unterminated modes for the SerDes channels. The FPGA monitors the communication mode requirements and dynamically adjusts the SerDes channel termination state accordingly - using terminated mode for high-speed communication and switching to unterminated mode for low-speed gears. This dynamic adaptability allows the same hardware channel to support both high-speed and low-speed UFS operations without requiring separate physical channels.
Data Source
AI summary
An automated test equipment (ATE) system comprises a system controller, wherein the system controller is communicatively coupled to a tester processor and an FPGA. The FPGA is communicatively coupled to the tester processor, wherein the FPGA is configured to internally generate commands and data transparently from the tester processor for testing a DUT. Further, the system comprises a demultiplexer positioned between the DUT and the FPGA, wherein, responsive to a determination that the DUT is operating in a high speed mode, the demultiplexer is configured to channel data traffic from the DUT to a Serializer/Deserializer (SerDes) receiver on the FPGA, and further wherein, responsive to a determination that the DUT is operating in a low speed mode, the demultiplexer is configured to channel data traffic from the DUT to input buffers on the FPGA with switchable on/off input terminations.