FPGA Base Caller Segregating Convolution Layers for CNN Acceleration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Deploying deep Convolution Neural Networks (CNNs) on portable and embedded systems is challenging due to large data volume, intensive computation, varying algorithm structures, and frequent memory accesses, which affects the efficiency of Graphics Processing Unit (GPU) and other general-purpose platforms, necessitating specialized acceleration hardware like Field Programmable Gate Arrays (FPGAs) for efficient convolution operations.
Innovation Solution
A neural network-based base caller system is developed using a configurable processor, such as an FPGA, which segregates processing of data for different sequencing cycles and employs segregated and combinatory convolution layers to efficiently handle convolution operations, enabling high-performance and flexible acceleration of CNN algorithms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If deep CNNs are deployed on general-purpose platforms like GPU, then the system can handle complex sequencing tasks, but the processing efficiency and power consumption are suboptimal due to intensive computation and frequent memory accesses
Solution Approach 1:
The patent segments the CNN processing into distinct functional blocks (convolution layers, pooling layers, fully connected layers) that can be independently configured and optimized on the reconfigurable processor, allowing each segment to be tailored for specific computational patterns in sequencing data
Solution Approach 2:
The reconfigurable processor allows dynamic reconfiguration of hardware architecture to match varying algorithm structures and data volumes in different sequencing tasks, enabling the system to adapt its computational resources in real-time rather than being fixed to a single configuration
2Speed
If specialized acceleration hardware like FPGA is used for convolution operations, then the processing speed and efficiency are improved, but the device complexity and development difficulty increase
Solution Approach 1:
The reconfigurable processor is designed with universal building blocks and modular architecture that can be configured to implement multiple CNN variants and sequencing algorithms, reducing development complexity by providing a standardized platform that handles diverse computational requirements through configuration rather than hardware redesign
3Productivity
If the neural network processes data for multiple sequencing cycles simultaneously, then the throughput is improved, but the memory access frequency and computational load increase significantly
Solution Approach 1:
The system performs preliminary processing and data preparation in advance of the main convolution operations, organizing sequencing data into optimized formats and pre-loading necessary parameters into on-chip memory, thereby reducing the computational burden and memory access frequency during the actual multi-cycle processing
Data Source
AI summary
A method of progressively training a base caller is disclosed. The method includes initially training a base caller, and generating labelled training data using the initially trained base caller; and (i) further training the base caller with analyte comprising organism base sequences, and generating labelled training data using the further trained base caller. The method includes iteratively further training the base caller by repeating step (i) for N iterations, which includes further training the base caller for N1 iterations of the N iterations with analyte comprising a first organism base sequence, and further training the base caller for N2 iterations of the N iterations with analyte comprising a second organism base sequence. A complexity of neural network configurations loaded in the base caller monotonically increases with the N iterations, and labelled training data generated during an iteration is used to train the base caller during an immediate subsequent iteration.