FPGA Interconnect Using BEOL DRAM Cells to Reduce Surface Area
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Solution Overview
Problem
Field-Programmable Gate Array (FPGA) devices face inefficiencies in semiconductor surface area usage due to the large number of transistors required for programmable interconnects, particularly in the Front-End-Of-Line (FEOL) process, where SRAM cells consume significant space.
Innovation Solution
The implementation of Dynamic Random Access Memory (DRAM) cells with select transistors and pass transistors in the Back-End-Of-Line (BEOL) portion of the FPGA, utilizing metal lines and semiconductor layers to reduce surface area consumption, with Indium Gallium Zinc Oxide (IGZO) as a preferred thin film semiconductor material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SRAM cells are used for storing the state of pass transistors in the FEOL, then the interconnect routing functionality is achieved, but the semiconductor surface area consumption is excessive
Solution Approach 1:
The patent extracts the memory function from the FEOL process by implementing DRAM cells in the BEOL metallization layers. This separates the logic block fabrication (FEOL) from the interconnect routing memory (BEOL), allowing SRAM cells to be replaced with more area-efficient DRAM structures that utilize available BEOL space
Solution Approach 2:
The patent transitions from planar SRAM cells in the FEOL to three-dimensional DRAM structures in the BEOL metallization layers. By stacking memory elements vertically across multiple metallization layers, the solution achieves higher density and reduces the footprint on the semiconductor surface
2Adaptability or versatility
If 6 pass transistors per interconnect point are implemented, then complete routing flexibility is achieved, but the transistor count and area consumption increase significantly
Solution Approach 1:
The patent uses DRAM cells to store the state of pass transistors, creating a compact memory representation of the routing configuration. Instead of requiring complex SRAM structures for each pass transistor state, the DRAM implementation provides a simplified copying mechanism that reduces overall device complexity while maintaining routing flexibility
Data Source
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AI summary
In an FPGA according to the invention, as in prior art FPGA's, programmable interconnect points are provided in the form of interconnect circuits comprising one or more pass transistors. In an FPGA according to the invention, at least some components of the interconnect circuits, and preferably all of said components are implemented in the Back end of Line part of the FPGA's production process, i.e. the part where metal interconnect layers are produced on the semiconductor substrate. In this way, the overall area consumed on the semiconductor surface is drastically reduced. Furthermore, the memory element in an interconnect point is not produced as an SRAM cell, but as a Dynamic Random Access Memory cell (DRAM cell), requiring only a single select transistor and (preferably) a storage capacitor for each memory element, instead of the 6 transistors of the SRAM cell. The fabrication of at least the select transistor and preferably also of the capacitor (if present) and the pass transistor involves the use of a suitable thin film semiconductor layer enabling to produce transistors with low leakage in the BEOL. A preferred choice for such thin film semiconductor material is Indium Gallium Zinc Oxide.