FPGA 3D Bin Packing With Parallel Alignment Evaluation
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Solution Overview
Problem
Existing methods for online 3D bin packing, such as heuristic approaches and deep reinforcement learning, face challenges in scalability and computational efficiency, particularly in large problems, due to limitations in Von Neumann architecture and the need for parallel and pipelined processing.
Innovation Solution
A method utilizing an FPGA-based system that performs parallel processing and pipelined execution for online 3D bin packing, involving a pre-trained DQN inference layer to identify feasible alignments and determine final placements of boxes within Long-Distance Containers (LDCs), leveraging parallel execution-pipeline architecture to evaluate multiple alignments efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If deep reinforcement learning is used for online 3D bin packing, then solution quality improves, but computational time and training complexity increase significantly
Solution Approach 1:
The patent pre-trains the deep Q-network model offline using historical data and simulated environments, storing the trained weights and biases in the FPGA's block RAM. This preliminary training action transfers the computational burden from online execution to offline preparation, allowing the FPGA to perform only inference operations during real-time bin packing, thus resolving the contradiction between solution quality and computational time
Solution Approach 2:
The patent replaces the traditional Von Neumann architecture-based CPU/GPU computing system with an FPGA-based parallel processing system. The FPGA's hardware parallelism and pipelined architecture substitute for sequential software execution, dramatically accelerating the inference process while maintaining solution quality, thereby addressing the computational time bottleneck
2Ease of operation
If CPU implementation is used for deep RL based bin packing, then ease of implementation is maintained, but processing speed is limited by Von Neumann architecture
Solution Approach 1:
The patent substitutes the Von Neumann architecture (sequential processing) with a dataflow architecture implemented on FPGA (parallel processing). The FPGA's inherent parallelism allows multiple operations to execute simultaneously, while the dataflow architecture enables data to flow through processing stages in a pipelined manner, both of which dramatically increase processing speed compared to traditional CPU implementation
3Measurement precision
If exhaustive evaluation of alignments is performed, then packing optimization improves, but computational complexity increases
Solution Approach 1:
The patent segments the alignment evaluation process into distinct computational stages implemented as separate modules in the FPGA: coordinate generation, dimension eligibility check, surface eligibility check, physical stability check, and feature determination. Each stage processes data independently and passes results to the next stage, enabling parallel execution and reducing overall computational complexity while maintaining exhaustive evaluation capability
Solution Approach 2:
The patent transforms the computational problem from a high-dimensional search space evaluated sequentially into a multi-stage pipeline where each stage handles a specific dimension of the problem. By organizing the evaluation into hierarchical stages (spatial checks → stability checks → feature extraction), the system reduces computational complexity through dimensional decomposition while still performing exhaustive evaluation
Data Source
AI summary
The disclosure generally relates to an FPGA-based online 3D bin packing. Online 3D bin packing is the process of packing boxes into larger bins-Long Distance Containers (LDCs) such that the space inside each LDC is used to the maximum extent. The use of deep reinforcement learning (Deep RL) for this process is effective and popular. However, since the existing processor-based implementations are limited by Von-Neumann architecture and take a long time to evaluate each alignment for a box, only a few potential alignments are considered, resulting in sub-optimal packing efficiency. This disclosure describes an architecture for bin packing which leverages pipelining and parallel processing on FPGA for faster and exhaustive evaluation of all alignments for each box resulting in increased efficiency. In addition, a suitable generic purpose processor is employed to train the neural network within the algorithm to make the disclosed techniques computationally light, faster and efficient.