FPGA Binary Neural Network Circuits With XNOR Popcount Neurons
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Solution Overview
Problem
Existing implementations of neural networks on programmable integrated circuits, such as FPGAs, are limited by resource constraints and power consumption, especially when trying to deploy large binary neural networks, which are typically software-based and inefficient in hardware form.
Innovation Solution
A hardware implementation of binary neural networks on FPGAs that maps neurons with high compute intensity, utilizing bitwise operations and specialized hardware neurons for efficient processing, reducing power consumption and routing resources by folding layers and neurons to optimize resource usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If binary neural networks are implemented in software on FPGAs, then flexibility and programmability are maintained, but processing speed and power efficiency deteriorate
Solution Approach 1:
The patent replaces software-based neural network processing with dedicated hardware circuits implemented on FPGA. The mechanical/software system is substituted with electronic/hardware circuits that perform bitwise operations (XNOR and population count) in parallel, achieving significant speedup while maintaining FPGA reconfigurability through programmable logic elements.
Solution Approach 2:
The patent changes the operational parameters of the neural network from floating-point or fixed-point arithmetic to binary representations with bitwise operations. This parameter transformation enables the network to operate efficiently in hardware by using XNOR gates for multiplication and population count circuits for accumulation, dramatically improving processing speed.
2Adaptability or versatility
If binary neural networks are implemented in software on FPGAs, then resource flexibility is maintained, but power consumption increases
Solution Approach 1:
The patent substitutes software execution with hardware circuit implementation, where dedicated logic circuits perform bitwise operations directly in parallel. This hardware substitution eliminates the overhead of software interpretation and execution, reducing power consumption while maintaining the ability to reconfigure the FPGA for different network architectures.
3Quantity of substance
If large binary neural networks are deployed on FPGAs, then network capacity increases, but routing resource requirements exceed available resources
Solution Approach 1:
The patent divides the large binary neural network into multiple layers and processing stages that can be systematically mapped to FPGA resources. By segmenting the network computation into discrete bitwise operation stages (XNOR layers followed by population count layers), the implementation can efficiently utilize FPGA routing resources while supporting large-scale networks.
Solution Approach 2:
The patent merges multiple computational operations into unified hardware circuits. Specifically, it combines the weight application and activation functions into single bitwise operation stages, and merges population count operations across multiple neurons to reduce overall routing requirements while maintaining network capacity.
Data Source
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AI summary
In an example, a circuit of a neural network implemented in an integrated circuit (IC) includes a layer (120) of hardware neurons (124), the layer including a plurality of inputs, a plurality of outputs, a plurality of weights, and a plurality of threshold values, each of the hardware neurons including: a logic circuit (302) having inputs that receive first logic signals from at least a portion of the plurality of inputs and outputs that supply second logic signals corresponding to an exclusive NOR (XNOR) of the first logic signals and at least a portion of the plurality of weights; a counter circuit (304) having inputs that receive the second logic signals and an output that supplies a count signal indicative of the number of the second logic signals having a predefined logic state; and a compare circuit (306) having an input that receives the count signal and an output that supplies a logic signal having a logic state indicative of a comparison between the count signal and a threshold value of the plurality of threshold values; wherein the logic signal output by the compare circuit of each of the hardware neurons is provided as a respective one of the plurality of outputs.