FPGA Binocular Camera Distortion Correction for 4K Real-Time Video

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Solution Overview

Problem

Traditional methods for binocular camera distortion correction in 3D endoscopic imaging face challenges with high resource consumption in FPGA BRAM and DDR memory, limiting the correction of high-resolution and large distortion images in real time.

Innovation Solution

A real-time high-resolution binocular camera distortion correction method using FPGA, involving YUV format processing, channel separation, distortion correction with interpolation, and ULTRA_RAM caching to optimize resource usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If traditional distortion correction method stores image in FPGA BRAM memory, then distortion correction can be performed, but more FPGA resources are consumed and only cameras with small distortion amplitudes or low image resolutions can be corrected

Engineering Contradiction:
Improvedistortion correction capabilityVSAvoidFPGA resource consumption
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent divides the image processing into separate channels (Y, U, V) and applies different processing strategies to each. The Y channel is processed without compression while U and V channels are compressed, allowing selective resource allocation and enabling higher resolution processing with optimized FPGA resource usage.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes the data representation parameters by converting to YUV format and applying compression to U and V channels. This parameter transformation reduces the data volume requiring storage resources while maintaining image quality, thereby enabling correction of larger distortions with fewer FPGA resources.

Inventive Principle:
Principle #35Parameter changes

2Manufacturing precision

If traditional camera distortion correction uses DDR memory, then more distortion can be corrected, but more DDR memory resources are occupied and overall system performance is reduced

Engineering Contradiction:
Improvedistortion correction capabilityVSAvoidsystem performance
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The patent replaces external DDR memory with on-chip FPGA memory resources (BRAM and URAM). This substitution eliminates the need for high-bandwidth external memory interfaces, reducing system complexity and improving overall performance while maintaining the capability to correct large distortions through optimized memory usage strategies.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent implements a multi-level memory hierarchy where compressed U and V channel data are stored in URAM (ultra RAM) within the FPGA, and Y channel data are processed in real-time without compression. This nested storage approach optimizes memory resource utilization and enables real-time processing of high-resolution videos with large distortions.

Inventive Principle:
Principle #7Nested doll (Nesting)

3Productivity

If high resolution and high frame rate videos are processed in real time, then better 3D imaging effect is achieved, but more FPGA resources are consumed and processing complexity increases

Engineering Contradiction:
Improvevideo processing throughputVSAvoidFPGA resource occupancy
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the video processing into separate Y, U, and V channel processing paths. By handling chroma subsampling and compression selectively on U and V channels while processing Y channel in real-time, the system achieves high frame rate processing of high resolution videos with optimized FPGA resource consumption.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies compression to U and V channels to reduce data volume, enabling real-time processing of high resolution videos. This parameter transformation maintains the 3D imaging effect while reducing the computational and resource burden on the FPGA system.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS12632942B2Real-time high-resolution binocular camera distortion correction implementation method based on FPGA
Publication Date: 2026.05.19 ZHUHAI DI PU MEDICAL TECH CO LTD
  • US12632942B2 patent drawing
  • US12632942B2 patent drawing
  • US12632942B2 patent drawing

AI summary

Provided in the present disclosure is a real-time high-resolution binocular camera distortion correction implementation method based on FPGA. The method includes acquiring input video information in a YUV format, and performing YUV channel separation on the input video information; compressing U and V video signals inputted; performing distortion correction on a Y video signal, and performing distortion correction on the compressed U and V video signals, including calculating binocular camera distortion parameters, calculating a coordinate mapping relationship of Y, U, and V channels, and calculating and generating target image data by using an interpolation algorithm; amplifying U and V target image data after distortion correction to fit an input image; and outputting separated Y, U, and V channel target image data according to a raw image format. According to the present disclosure, high resolution and high frame rate videos can be processed in real time.