FPGA BiSS Decoder Interface With CRC for Stable Position Data
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Solution Overview
Problem
Conventional BISS protocol data decoding methods for absolute grating rulers are inflexible and unable to provide multiple functions, limiting high-speed and high-stability data processing.
Innovation Solution
A method and interface system utilizing an FPGA chip with an MA drive module, an SL receiving module, and a CRC check module for BISS protocol data decoding, which includes receiving an enable signal, transmitting an MA clock signal, detecting a trigger signal, reading SL data, performing CRC checks, and outputting correct position values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional BISS protocol data decoding methods are used, then the implementation is simple, but the data processing flexibility and functional versatility are limited
Solution Approach 1:
The patent implements a universal decoding architecture that can handle multiple communication protocols (BISS, SSI, EnDat) and multiple communication modes (Sensor Mode, Register Mode, Bidirectional Mode) within a single system. The FPGA-based design provides flexible configuration capabilities that allow the same hardware platform to adapt to different protocol requirements and functional needs, thereby achieving multi-functionality without requiring separate dedicated decoders for each protocol.
Solution Approach 2:
The patent employs dynamic configuration capabilities where the decoding parameters, data length, time length, and communication mode can be adjusted in real-time based on the specific application requirements. The system can dynamically switch between different protocols and modes of operation, allowing the decoding method to adapt flexibly to changing operational conditions rather than being fixed to a single configuration.
2Productivity
If high-speed data reception is implemented for absolute grating rulers, then the machining efficiency improves, but the data transmission stability and accuracy may be compromised
Solution Approach 1:
The patent implements comprehensive error detection and correction mechanisms including CRC (Cyclic Redundancy Check) verification for data integrity validation. The system continuously monitors the received data for errors and can request retransmission or correct errors automatically, ensuring that high-speed data transmission does not compromise accuracy. This feedback mechanism maintains reliability even as transmission speed increases.
Solution Approach 2:
The patent incorporates proactive error prevention measures by implementing robust data validation protocols before data processing occurs. The CRC check and other verification mechanisms are built into the data reception process to prevent corrupted data from affecting subsequent operations, thereby cushioning against potential transmission errors that could occur at high speeds.
3Speed
If the BISS protocol baud rate is increased to 10 MHz for high-speed communication, then the data transmission speed improves, but the signal interference and error rate may increase
Solution Approach 1:
The patent employs real-time error monitoring and detection mechanisms that actively scan for signal interference and transmission errors. When errors are detected at high baud rates, the system can adjust transmission parameters or request retransmission, thereby maintaining data integrity even at 10 MHz transmission speeds where signal interference is more likely to occur.
Data Source
AI summary
There are provided a method and an interface system for Bidirectional Synchronous Serial (BISS) protocol data decoding. The method includes: an MA drive module receiving an enable signal en and transmitting an MA clock signal to an SL receiving module, and then the SL receiving module detecting a trigger signal of SL; when a start bit of the SL is detected by the SL receiving module, the SL receiving module reading SL data; after the SL data is read, the SL receiving module transmitting a done signal to the MA drive module to stop operation of the MA drive module and transmitting a did signal to a CRC check module; and after the did signal is received by the CRC check module, the CRC check module performing CRC check on the SL data and outputting a correct position value after the check is completed.