FPGA Memory BIST via Dedicated Configuration Bus
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Solution Overview
Problem
Existing built-in self-test (BIST) techniques for field-programmable gate arrays (FPGAs) fail to achieve worst-case stress conditions for embedded memory testing due to latency in fabric routing, leading to potential defective parts being shipped and inefficient resource utilization, which results in lower-speed designs and increased test time and cost.
Innovation Solution
Implementing a 'shadow-BIST' capability with a memory BIST engine in the configuration logic that allows back-to-back configuration and read-back operations at higher than at-speed frequencies, utilizing an embedded phase-lock loop (PLL) to generate twice the configuration frequency, thereby stressing memory cells effectively without adding overhead to the configuration time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fabric-based BIST testing is used to test FPGA embedded memory at rated frequency, then memory testing can be performed, but latency in fabric routing prevents achievement of worst-case stress conditions and leads to defective parts being shipped
Solution Approach 1:
The patent extracts the BIST controller from the fabric-based approach and places it directly in the configuration logic, removing it from the fabric routing path. This eliminates the latency introduced by fabric routing and allows direct control of the embedded memory block, achieving worst-case stress conditions while maintaining reliable testing.
Solution Approach 2:
The patent introduces a dedicated configuration logic interface as an intermediary between the BIST controller and the embedded memory block. This intermediary provides direct, low-latency access to the memory block without going through fabric routing, enabling accurate stress condition application while maintaining testing reliability.
2Adaptability or versatility
If multiple BIST masters are created to test hundreds of embedded memory blocks, then comprehensive memory coverage is achieved, but resource utilization creates congestion and results in lower-speed design
Solution Approach 1:
The patent implements a single BIST controller in the configuration logic that can universally test multiple embedded memory blocks. This single controller provides multi-functional capability to test hundreds of memory blocks without requiring multiple separate BIST masters, thereby avoiding fabric congestion and maintaining design speed while achieving comprehensive memory coverage.
3Ease of operation
If fabric routing is used for BIST testing, then memory blocks can be accessed, but delay is added to programmable routes resulting in lower-speed design
Solution Approach 1:
The patent extracts the BIST control function from the fabric routing path and places it directly in the configuration logic. This removes the memory block access function from the fabric routing domain, eliminating the associated delays while maintaining ease of operation through direct configuration logic control.
Solution Approach 2:
The patent performs memory testing during the configuration phase before the device enters normal operation. By utilizing the configuration logic's inherent access capabilities, the testing is performed preliminarily without requiring additional routing resources or introducing delays to the operational fabric routes.
4Productivity
If configuration frequency is used for memory testing, then testing can be performed without additional overhead, but the frequency is lower than the memory's rated frequency reducing test effectiveness
Solution Approach 1:
The patent dynamically adjusts the testing frequency to match the embedded memory block's rated frequency rather than being constrained by the configuration frequency. The BIST controller in the configuration logic can generate test patterns at the memory's operational frequency, providing dynamic frequency adaptation that ensures both test efficiency and reliability.
Solution Approach 2:
The patent changes the frequency parameter of the test signals from the configuration frequency to the embedded memory's rated frequency. By modifying this critical parameter, the testing becomes effective for high-frequency memory blocks while the configuration logic maintains its role as the control interface, achieving both efficiency and reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high-stress testing of FPGAs with zero delay penalty, effectively screening defective RAM bits and ensuring low defect levels, even in harsh environments, while maintaining design speed and reducing test costs.
Implementation Method 1
utilizing an embedded phase-lock loop (PLL) to generate twice the configuration frequency
Data Source
AI summary
In one embodiment, a BIST (built-in self-test) engine performs BIST testing of embedded memory in an integrated circuit device (e.g., an FPGA) via an (e.g., hard-wired, dedicated, low-latency) bus from the configuration bitstream engine. During BIST testing, data is written into the embedded memory at-speed, which may require the bitstream engine to produce a higher frequency than originally used for configuration. Between consecutive write operations, the BIST engine is capable of reading the previously written set of data from the embedded memory and comparing that read-back data with the corresponding original set of data to determine whether a BIST error has occurred. By performing back-to-back write/read-back operations faster than the configuration speed and using a dedicated W/RB bus, BIST testing can be optimally performed without false-positive-invoking delays and undesirable resource utilization.