FPGA Built-In Self-Test With Circular Self-Test Path
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Solution Overview
Problem
Current FPGA designs lack a built-in self-test mechanism with high fault coverage, which can lead to system failures in mission-critical applications, and existing BIST solutions are technology-dependent, burdensome, and not suitable for startup tests, especially in military and aerospace fields.
Innovation Solution
A low-cost, technology-independent FPGA BIST scheme using a circular self-test path (CSTP) structure that isolates primary inputs and outputs, employs linear feedback shift registers for test pattern generation, and includes multiple signature output taps to improve fault coverage and reduce implementation overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple programming files are used for exhaustive testing of FPGA logic fabrics, then fault coverage is improved, but design complexity and implementation burden increase
Solution Approach 1:
The patent segments the FPGA device into multiple regions, with at least one region designated as a self-test region that can be independently configured and tested. This segmentation allows the test infrastructure to be localized within specific regions rather than requiring device-wide reconfiguration, thereby reducing the complexity burden of multiple programming files while maintaining comprehensive fault coverage across the entire device.
2Difficulty of detecting and measuring
If TPG and ORA are implemented to test FPGA resources, then fault detection capability is improved, but the burden on designer and multiple programming files are required
Solution Approach 1:
The patent implements self-service by enabling the FPGA device to test itself through built-in self-test regions that contain test pattern generators and response analyzers. These self-test regions can be automatically configured and executed without requiring external test equipment or complex designer intervention, thereby improving fault detection capability while reducing designer burden and eliminating the need for multiple separate programming files.
3Manufacturing precision
If offline testing schemes are used for FPGA logic blocks, then manufacturing testing is improved, but system level and field tests are not suitable
Solution Approach 1:
The patent creates a universal test infrastructure by designing self-test regions that can function in multiple modes: manufacturing testing mode for initial device characterization, system-level testing mode for integration verification, and field testing mode for operational reliability assessment. This multi-functionality is achieved through configurable test regions that can be programmed with different test patterns and analysis parameters, allowing the same hardware infrastructure to serve diverse testing needs across the device lifecycle.
4Reliability
If roving self-testing areas with dynamic partial reconfiguration are implemented, then fault-tolerance is improved, but device complexity and programming file requirements increase
Solution Approach 1:
The patent applies preliminary action by pre-configuring dedicated self-test regions during device fabrication or initial programming, rather than requiring dynamic reconfiguration during operation. These pre-established test regions contain all necessary test pattern generators and response analyzers ready for immediate activation, eliminating the need for complex runtime reconfiguration operations while maintaining high fault-tolerance capabilities through persistent test infrastructure.
Data Source
AI summary
A system and method for designing a field programmable gate array (FPGA) with built-in test mechanism includes several enhancements to traditional circular self-test path (CSTP) BIST architecture. The FPGA BIST scheme isolates primary inputs and primary outputs to improve test coverage. Multiple signature output taps are inserted at CSTP registers throughout the test path to help improve signature aliasing probability. Enhanced CSTP register selection algorithms help prevent register adjacency problems and optimize overall resource utilization for implementation. Multiple clock domains are also handled by the FPGA BIST to allow full chip implementation of the FPGA BIST.