FPGA Bitfile Upgrade via CPLD and Dual-Section FLASH Memory
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Solution Overview
Problem
Existing FPGA upgrade methods are unreliable due to the need for multiple EEPROMs, which occupy valuable PCB space and can result in system failure if bit file upgrades through the PCI interface fail, especially in systems without a GPIO channel.
Innovation Solution
A system and method that uses a FLASH memory to store both workable and backup versions of FPGA bit files, with a CPLD to download and manage these files, communicating with the CPU to ensure successful upgrades and maintain system functionality by switching between versions if necessary.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple EEPROMs are used to store large FPGA bit files, then the bit file storage capacity is sufficient, but the PCB space is occupied and system reliability is reduced
Solution Approach 1:
The patent combines multiple EEPROMs into a single FLASH memory device to store large FPGA bit files. This merging approach provides sufficient storage capacity while reducing the number of components on the PCB, thereby improving system reliability and reducing board space occupation.
Solution Approach 2:
The FLASH memory device serves multiple functions: it stores both the working bit files and backup bit files, replacing the need for multiple separate EEPROMs. This multi-functional approach maintains adequate storage capacity while simplifying the system architecture and improving reliability.
2Ease of operation
If bit files are upgraded through the PCI interface implemented by FPGA, then no GPIO channel is needed, but the system loses total functionality if the upgrade fails
Solution Approach 1:
The patent implements preliminary action by writing backup bit files to the FLASH memory before performing the actual upgrade. This preparatory step ensures that if the upgrade process fails, the system can revert to the backup version, thereby maintaining upgrade reliability while using the simple PCI interface approach.
Solution Approach 2:
The patent provides beforehand cushioning by maintaining backup bit files in the FLASH memory as a safety net. This protective measure cushions against potential upgrade failures, allowing the system to recover functionality by switching to the backup version if the primary upgrade fails.
3Reliability
If a single FLASH memory is used to store bit files, then PCB space is reduced and reliability is improved, but there is no backup version for failed upgrades
Solution Approach 1:
The patent segments the FLASH memory into different regions: one for storing working bit files and another for storing backup bit files. This segmentation allows the single FLASH device to provide both reliability through consolidation and adaptability through backup capability, enabling upgrade recovery when needed.
Solution Approach 2:
The patent utilizes parameter changes by dynamically switching between different bit file versions stored in the FLASH memory. The system can change the active bit file version parameter based on upgrade success or failure, providing both reliable operation and the ability to recover from failed upgrades using the same consolidated storage device.
Data Source
AI summary
A system for FPGA (Field Programmable Gate Array) upgrade includes: an FPGA, a FLASH memory and a CPLD. The FLASH memory includes a first section configured to store a workable version of bit files for the FPGA and a second section configured to store a backup version of bit files for the FPGA. The CPLD is coupled to the FPGA and the FLASH memory. The CPLD is configured to download the bit files from the FLASH memory to the FPGA to provide the FPGA with functionality. As a result, the CPLD communicates with CPU to upgrade the bit files in the FLASH memory, and indicates to the CPU which version of bit files has been downloaded to the FPGA.