FPGA Configuration Bitstream Compression Using 2D Block Transforms
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Solution Overview
Problem
The growing size of configuration data for programmable logic devices (PLDs) imposes usability limitations due to increased memory demands and configuration time, as previous compression methods do not effectively utilize the two-dimensional block structure of FPGAs, leading to suboptimal compression ratios.
Innovation Solution
A method and system that apply two-dimensional transformations followed by one-dimensional compression to configuration data streams for FPGAs, utilizing inter-block and intra-block transformations to create a block-fingerprint library and bitmaps, and then applying one-dimensional compression to achieve higher compression ratios, and a decompression module for reverse transformation to regenerate the original data stream.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional one-dimensional compression methods are used on configuration data streams, then the compression process is simple, but the compression ratio is suboptimal leading to larger configuration data size
Solution Approach 1:
The patent transforms the configuration data stream from a one-dimensional sequence into a two-dimensional matrix structure, where rows represent logic array blocks and columns represent bit positions. This dimensional transformation enables the application of 2D compression algorithms that can exploit both horizontal (intra-block) and vertical (inter-block) redundancies in the data, significantly improving compression ratios compared to traditional 1D methods.
2Quantity of substance
If two-dimensional transformations are applied to configuration data, then higher compression ratios are achieved, but the processing complexity increases
Solution Approach 1:
The patent performs 2D transformations and compression operations on the configuration data stream before it is loaded into the FPGA's configuration memory. By pre-compressing the data and storing it in a compressed state, the actual configuration time when the FPGA needs to be programmed is reduced, as the decompression can occur in parallel with or before the configuration process begins.
3Volume of stationary object
If configuration data is compressed to reduce memory demands, then storage requirements are reduced, but decompression processing is required
Solution Approach 1:
The patent implements a decompression module within the FPGA device itself that can autonomously decompress the compressed configuration data stream. This self-service approach allows the FPGA to decompress its own configuration data without requiring external assistance, reducing the need for additional external decompression hardware or software tools.
Data Source
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AI summary
One embodiment relates to a method (300) for compressing a data-stream of configuration data for electronically configuring an electronically-programmable semiconductor device having a two-dimensional (2D) block structure for an array of core resources. Inter-block and intra-block transformations (316, 316; 322) may be applied to the data-stream to obtain a 2D-transformed data-stream which can be shorter and/or more compressible than the original data. Subsequently, one-dimensional (1D) compression (324) that considers the configuration data as a sequence of bits (and does not consider the 2D block structure) may be applied to obtain a final compressed data sequence that is streamed to the electronically-programmable semiconductor device. Another embodiment relates to a method of decompressing the compressed data-stream of configuration data that is received by the semiconductor device. Other embodiments, aspects, and features are also disclosed.