FPGA Bitstream Storage for Daisy-Chain Programming
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Solution Overview
Problem
Current programmable gate array systems, such as IOCNET, are limited in their ability to integrate FPGAs from third-party suppliers due to the need for specific native design for programming, which restricts adaptability and customer requirements.
Innovation Solution
A configurable first configuration logic on a programmable gate array is implemented to receive a user bitstream, store it in non-volatile memory, and configure user logic, allowing integration of third-party FPGAs without dedicated programming interfaces, enabling daisy chain configurations and resource conservation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If FPGAs are programmed via dedicated JTAG interfaces, then programming reliability is improved, but device complexity and cable requirements increase
Solution Approach 1:
The patent makes regular data lines serve dual purposes: both for data exchange during system operation and for programming FPGAs. This eliminates the need for separate dedicated programming interfaces and cables, reducing device complexity while maintaining programming capability through the existing multi-functional data lines
2Device complexity
If FPGAs are programmed over regular data lines in IOCNET, then device complexity is reduced, but adaptability to third-party FPGAs worsens
Solution Approach 1:
The patent implements a self-service mechanism where each FPGA contains configuration logic that automatically receives bitstreams through the regular data lines and configures itself without requiring native IOCNET design or additional external programming hardware. This enables third-party FPGAs to be integrated and programmed through the existing data lines, improving adaptability while maintaining low device complexity
3Ease of operation
If additional CPLD is integrated on all FPGA expansion cards for programming, then programming capability is improved, but loss of substance increases
Solution Approach 1:
The patent extracts the programming function from external dedicated programming hardware (CPLD) and integrates it directly into the FPGA's configuration logic. This eliminates the need for separate programming components on expansion cards, reducing hardware resource consumption while maintaining full programming capability through the regular data lines
Data Source
AI summary
To program a first programmable gate array, for example a first FPGA, in a distributed computer system, a configuration of a first configuration logic on the first programmable gate array is provided. The first configuration logic is configured to receive a first user bitstream from a configuration software for configuring a first user logic on the first programmable gate array and to store the first user bitstream on a non-volatile memory of the first programmable gate array for the purpose of subsequently configuring a first user logic on the first programmable gate array according to the specifications from the first user bitstream. In an expansion stage of the invention, a configuration of a programming logic on the first programmable gate array is also provided for programming a second programmable gate array, which is connected to the first programmable gate array to form a daisy chain.