FPGA Bitstream Validation Using On-Device Partition Masks

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Solution Overview

Problem

Existing methods for validating configuration data on programmable devices, such as FPGAs, often rely on external validation which can compromise security and complexity, and may result in unintended programming of non-permitted device portions.

Innovation Solution

Implementing on-device validation checks using configuration hardware, including secure device managers and local sector managers, to verify that configuration data is correctly programmed within permitted areas without exposing sensitive information, through techniques like linear-feedback shift registers and masks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If external validation methods are used to verify configuration data, then validation can be performed, but security is compromised and device complexity increases

Engineering Contradiction:
Improveconfiguration validationVSAvoidvalidation system complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The configuration validation system performs self-verification using on-device check values and authentication bitstreams. The device autonomously validates its own configuration data without requiring external validation infrastructure, thereby maintaining security while reducing system complexity.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

Authentication bitstreams serve as intermediaries between the configuration data and validation process. These bitstreams contain encoded verification information that enables validation without exposing sensitive configuration details or requiring complex external validation systems.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If configuration data is validated externally, then validation capability is provided, but sensitive information may be exposed

Engineering Contradiction:
Improveconfiguration validationVSAvoidinformation exposure risk
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The validation mechanism extracts only the necessary verification information into authentication bitstreams, which are then used for validation. This extraction process allows validation to occur without exposing the complete sensitive configuration data, as only authenticated summaries are transmitted or processed.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

Instead of validating the original sensitive configuration data directly, the system uses copied authentication information stored in authentication bitstreams. These copies contain sufficient verification data without revealing the actual configuration secrets, thereby enabling validation while protecting sensitive information.

Inventive Principle:
Principle #26Copying

3Reliability

If on-device validation is implemented, then security is enhanced and reliance on external environments is reduced, but device complexity increases

Engineering Contradiction:
Improveconfiguration securityVSAvoidon-device validation complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The validation functionality is merged with the existing configuration hardware resources on the device. By combining validation operations with the configuration pipeline and utilizing existing logic elements, the system achieves enhanced security without proportionally increasing device complexity.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The configuration hardware is designed to perform multiple functions: both configuration loading and validation operations. This multi-functionality allows the same hardware resources to serve dual purposes, reducing the need for dedicated validation hardware and thereby limiting the increase in device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

4Productivity

If configuration hardware is used for validation, then validation efficiency is improved, but the same hardware resources are required for both configuration and validation

Engineering Contradiction:
Improvevalidation efficiencyVSAvoidhardware resource utilization
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The validation process is implemented as a periodic operation that occurs during the configuration loading sequence. The configuration hardware alternates between loading configuration data and performing validation checks, utilizing the same hardware resources in a time-multiplexed manner to achieve efficient validation without requiring duplicate hardware.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The hardware resource allocation is made dynamic, allowing the configuration logic to switch between configuration and validation modes. This dynamic utilization enables the same hardware to efficiently handle both functions by adapting its operation based on the current phase of the configuration process.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS11562101B2On-device bitstream validation
Publication Date: 2023.01.24 ALTERA CORP
  • US11562101B2 patent drawing
  • US11562101B2 patent drawing
  • US11562101B2 patent drawing

AI summary

A programmable logic device verifies that configuration data permissibly programs the programmable logic device. The programmable logic device includes a programmable fabric having partitions to be programmed by the configuration data, a secure device manager that may generate masks based on the configuration data, and a local sector manager. The masks determine that the configuration data is configured to permissibly program the permitted partitions or that the permitted partitions have been permissibly programmed. The local sector manager applies the masks to generate an interleaved result, compares the interleaved result to an expected result, and sends an indication that the configuration data is configured to permissibly program the permitted partitions or permissibly programmed the permitted partitions in response to determining that the interleaved result is the expected result, or sends an alert to stop programming in response to determining that the interleaved result is not the expected result.