Bitstream Stitching for Fast FPGA Compilation
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Solution Overview
Problem
The long compilation time for programmable logic devices, such as high-capacity FPGAs, hinders market traction and increases development costs and time, especially with complex designs, due to the computational and resource-intensive nature of fine-grained operations.
Innovation Solution
Implementing coarse-grained operations by stitching pre-compiled regional bitstreams into a combined bitstream, which reduces compilation time and storage requirements, using techniques like network-on-chip (NOC) for efficient data transport and spatial decoupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If fine-grained operations are used for high-capacity FPGA designs, then design functionality and complexity are improved, but compilation time and computational resource requirements increase significantly
Solution Approach 1:
The patent divides the FPGA design into multiple regional bitstreams, each representing a specific region or module of the device. These regional bitstreams can be compiled independently and then stitched together during configuration, reducing the overall compilation time compared to compiling the entire design as a single fine-grained bitstream.
Solution Approach 2:
The patent pre-compiles regional bitstreams before the final device configuration. By preparing and storing these pre-compiled regional bitstreams in a library, the system eliminates the need to re-compile the entire design from scratch during each configuration process, significantly reducing configuration time.
2Adaptability or versatility
If fine-grained operations are used for high-capacity FPGA designs, then design functionality and complexity are improved, but computational and resource intensity increase
Solution Approach 1:
The patent segments the compilation process into independent regional bitstream compilations. Each region can be compiled separately using appropriate computational resources, and the results are stored for later use. This segmentation reduces the peak computational resource requirements compared to compiling the entire fine-grained design at once.
Solution Approach 2:
The patent creates a library of pre-compiled regional bitstreams that can be reused across different device configurations. By storing and reusing these pre-compiled regions, the system avoids redundant computational work and reduces the overall computational resource intensity required for subsequent design implementations.
3Loss of time
If pre-compiled regional bitstreams are stitched together, then compilation time is reduced, but device complexity increases due to stitching mechanisms
Solution Approach 1:
The patent introduces a configuration manager as an intermediary component that handles the stitching process. This manager receives pre-compiled regional bitstreams, determines their appropriate placements within the device architecture, and coordinates their integration. This intermediary abstraction simplifies the overall system by centralizing the complexity of bitstream stitching in a dedicated management function.
Data Source
AI summary
Systems or methods of the present disclosure may provide a library including multiple regional bits streams that may be pre-generated by a manufacturer and/or custom generated by a designer that may be used to implement a design onto an integrated circuit device. The design may be decomposed into one or more regional bitstreams and stitched to form a larger combined bitstream to be implemented as coarse-grained operations on the integrated circuit device, thereby decreasing compilation time experienced by the designer. The combined bitstreams may be loaded into all or a portion of the integrated circuit device to realize the design. Additionally or alternatively, the integrated circuit device may include a hardened networks-on-chip to improve data routing within the combined bitstream.