Striping Data in FPGA BlockRAM to Prevent Switch Collisions
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Solution Overview
Problem
Traditional network switches, especially those using ASICs, are limited in supporting diverse communication protocols and require significant logic resources, making them inflexible and inefficient in terms of memory usage, particularly when handling different data protocols on Field Programmable Gate Arrays (FPGAs).
Innovation Solution
A protocol-agnostic cell-based switch utilizing BlockRAM memory on FPGAs with a scalable memory architecture, pipelining, and class queues that eliminate the need for addressing, allowing for flexible protocol support with minimal logic resources by using a small amount of BRAM and efficiently managing data storage and retrieval through programmable port data-paths and error handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional ASIC-based network switches are used to support specific protocols, then switching performance is improved, but adaptability to different protocols deteriorates
Solution Approach 1:
The patent implements a universal memory-based switching architecture that can handle multiple data protocols (Ethernet, InfiniBand, PCI Express, etc.) through a single reconfigurable system. The memory buffer and arbitration logic are designed to be protocol-agnostic, allowing the same hardware infrastructure to support diverse protocols without requiring separate dedicated switching paths for each protocol type.
Solution Approach 2:
The system employs dynamic reconfiguration capabilities where the switching fabric can adapt its behavior based on the active protocol. The arbitration mechanism dynamically selects between different data formats and protocols, and the memory access patterns are dynamically adjusted based on protocol requirements, enabling the system to optimize performance for each protocol while maintaining support for others.
2Adaptability or versatility
If memory-based switching with buffering is implemented to support multiple protocols, then protocol versatility is improved, but logic resource consumption deteriorates
Solution Approach 1:
The patent divides the memory buffer into multiple segments or banks that can be independently managed. Each segment can be allocated to handle specific protocol traffic or data flows, allowing parallel processing of multiple protocols simultaneously. This segmentation reduces the complexity of arbitration logic by breaking down the monolithic switching function into smaller, more manageable units that can operate semi-independently.
Solution Approach 2:
The patent introduces a memory buffer as an intermediary element between input and output ports. This memory-based mediation layer decouples the direct path between inputs and outputs, allowing protocol translation and arbitration to occur in the memory domain rather than requiring complex real-time logic circuits. The memory acts as a buffer that absorbs protocol-specific processing requirements, reducing the logic resource burden on the switching fabric itself.
3Quantity of substance
If extensive memory resources are allocated for data buffering, then data storage capacity is improved, but available FPGA resources for additional nodes deteriorates
Solution Approach 1:
The patent merges the switching fabric, memory buffer, and arbitration logic into a single integrated memory-based switching system. By combining these functions into a unified architecture rather than separate components, the system achieves efficient resource utilization where the same memory resources serve multiple purposes (buffering, routing, and protocol handling), thereby maximizing the utility of limited FPGA resources while maintaining full switching functionality.
Solution Approach 2:
The system employs parameterizable memory configurations where the buffer size, number of banks, and arbitration depth can be adjusted based on specific application requirements. This allows the memory resources to be optimized for the actual traffic patterns and protocol requirements of the deployed system, ensuring that sufficient buffering capacity is provided without over-provisioning that would waste valuable FPGA resources. The parameters can be tuned to achieve the minimum necessary memory capacity for the given workload.
Data Source
AI summary
A shared memory switch is provided for storing and retrieving data from BlockRAM (BRAM) memory of a PLD. A set of class queues maintain a group of pointers that show the location of the incoming “cells” or “packets” stored in the memory in the switch based on the time of storage in the BRAM. A non-blocking memory architecture is implemented that allows for a scalable N×N memory structure to be created (N=number of input and output ports). A write controller stripes the data across this N×N memory to prevent data collisions on read in or read out of data. The data is scheduled for read out of this N×N shared memory buffer based on priorities or classes in the class queues, with priorities being set by a user, and then data is read out from the BRAM.