FPGA User Logic Boundary Scan Chain Generation
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Solution Overview
Problem
Current boundary scan test methods are time-consuming and inflexible due to the need for hardware implementation, requiring testing of all pads, which limits efficiency and flexibility.
Innovation Solution
A method that generates a boundary scan chain using user logic to test connectivity, allowing for software configuration of FPGA to test specific pads without unnecessary hardware upgrades, shortening test chains and enabling rapid and flexible testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If boundary scan test is implemented by hardware, then test coverage is complete, but test time is long and test arrangement is inflexible
Solution Approach 1:
The patent replaces hardware-based boundary scan test with software-based implementation using FPGA user logic. Instead of using dedicated hardware boundary scan units, the invention uses software algorithms running on FPGA to achieve the same testing function, thereby reducing test time and increasing flexibility while maintaining test coverage.
Solution Approach 2:
The invention changes the implementation parameter from hardware to software. By configuring FPGA user logic to generate boundary scan chains dynamically, the system can adapt test arrangements flexibly and reduce test time without sacrificing complete test coverage of all PADs.
2Reliability
If boundary scan test is implemented by hardware, then test coverage is complete, but test arrangement flexibility is reduced
Solution Approach 1:
The patent implements dynamic test arrangement capability through software configuration. The FPGA user logic can be programmed to create different boundary scan chain configurations based on testing requirements, allowing flexible adaptation to various test scenarios while maintaining complete coverage of all PADs.
Solution Approach 2:
By changing from fixed hardware implementation to software-based FPGA configuration, the system gains the ability to dynamically adjust test arrangements. The user logic can be reconfigured to test different PAD subsets or create customized scan chains, significantly improving adaptability while preserving comprehensive test coverage.
3Reliability
If all PADs are tested using hardware boundary scan, then complete testing is achieved, but test efficiency is reduced
Solution Approach 1:
The invention replaces slow hardware boundary scan with faster software-based FPGA testing. By using FPGA user logic to generate and execute test sequences, the system achieves complete testing of all PADs with significantly improved test efficiency and reduced testing time.
Solution Approach 2:
The patent implements preliminary configuration of test sequences and boundary scan chains in FPGA user logic before actual testing. This pre-preparation allows for optimized test execution that maintains complete coverage while improving efficiency through sophisticated software-controlled test scheduling and vector generation.
Data Source
AI summary
A boundary scan test method is used to test connectivity of a pad having a direct connection to user logic. The method comprises the following steps: configuring an FPGA to enter a test mode; generating by means of user logic, a boundary scan chain for a boundary scan test; loading a boundary scan test instruction to the FPGA, and loading a PRELOAD instruction to a device having a pad to be tested for connectivity; sending, via a TDI port, a first test vector to the pad; performing the boundary scan test, and loading an EXTEST instruction to the device having the pad; and removing first response data from a TDO port, and performing response analysis and fault diagnosis.