FPGA BRAM ECC Testing Using Ring-Connected Memory Blocks
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Solution Overview
Problem
Existing methods for testing the Error Correcting Code (ECC) function of Field Programmable Gate Array (FPGA) on-chip block random access memory (BRAM) require a large number of test stimuli and frequent interactions with the upper computer port, making the process inefficient, especially when dealing with a large number of BRAMs.
Innovation Solution
A system and method that utilizes the internal logic of the FPGA and data preset in the BRAM to test the ECC function, reducing the need for test stimuli and interactions with the upper computer port by connecting BRAMs in a ring structure and using parity bit comparison modules to verify parity bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing techniques are used to test BRAM with ECC function, then the ECC function can be tested, but a large number of test stimuli and frequent interactions with the upper computer port are required, making the test very inefficient
Solution Approach 1:
The patent combines multiple BRAM modules into a ring-structured test system where data flows sequentially through each module. This merging approach allows simultaneous testing of multiple BRAM units with a single test stimulus sequence, eliminating the need for separate testing of each module and significantly improving test efficiency while maintaining comprehensive ECC function verification.
Solution Approach 2:
The patent implements preliminary action by pre-loading test data into the first BRAM module before the test sequence begins. The ring structure is pre-configured with the necessary control logic and data paths, allowing the test to proceed automatically through all modules without requiring real-time external intervention or stimulus generation for each module.
2Reliability
If a large number of BRAMs are tested using existing methods, then comprehensive coverage is achieved, but the number of test stimuli and interactions with the upper computer port increases significantly
Solution Approach 1:
The patent segments the test system into a ring-structured configuration where BRAM modules are arranged in sequence. Each module processes a portion of the test data independently but contributes to the overall test coverage. This segmentation allows comprehensive testing of multiple modules while using a unified, simplified control approach that reduces the complexity of test stimulus generation and management.
Solution Approach 2:
The ring-structured test system implements universality by using a single test data flow that serves multiple BRAM modules simultaneously. The same test stimulus sequence can verify ECC functions across all modules in the ring, making the test system multi-functional and capable of testing any number of BRAM units without proportionally increasing test complexity.
Data Source
AI summary
A system and method for testing Error Correcting Code (“ECC”) function of Field Programmable Gate Array (“FPGA”) on-chip block random access memory (“BRAM”) includes control modules, at least two BRAMs with ECC function and sequentially connected to form a ring, and parity bit comparison modules corresponding to each BRAM. Each parity bit comparison module is connected to its corresponding BRAM and the next adjacent BRAM. The control module is used to send data read and write test instructions to each BRAM. Each BRAM is used to read test data sequentially, write test data into next adjacent BRAM whenever the test data is read, and send the first parity bit generated during reading to the corresponding parity bit comparison module. Each parity bit comparison module is used to compare the first and second parity bits, where the second parity bit is generated during the writing of test data. The embodiments of the present invention reduce the required test stimuli and the interactions with upper computer ports, which enhances the test efficiency.